LPC2926_27_29 NXP Semiconductors, LPC2926_27_29 Datasheet - Page 60

• Manufacturer Part Number: LPC2926_27_29
• Description: The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2926_27_29
Product data sheet
6.17.1 Functional description
6.17.2 Clock description
The Vectored Interrupt Controller routes incoming interrupt requests to the ARM
processor. The interrupt target is configured for each interrupt request input of the VIC.
The targets are defined as follows:
Interrupt-request masking is performed individually per interrupt target by comparing the
priority level assigned to a specific interrupt request with a target-specific priority
threshold. The priority levels are defined as follows:
Software interrupt support is provided and can be supplied for:
The VIC is clocked by CLK_SYS_VIC, see
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Target 0 is ARM processor FIQ (fast interrupt service).
Target 1 is ARM processor IRQ (standard interrupt service).
Priority level 0 corresponds to ‘masked’ (i.e. interrupt requests with priority 0 never
lead to an interrupt).
Priority 1 corresponds to the lowest priority.
Priority 15 corresponds to the highest priority.
Testing RTOS (Real-Time Operating System) interrupt handling without using
device-specific interrupt service routines.
Software emulation of an interrupt-requesting device, including interrupts.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 28 September 2010
ARM9 microcontroller with CAN, LIN, and USB
Section
LPC2926/2927/2929
6.7.2.
© NXP B.V. 2010. All rights reserved.
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