LPC2926_27_29 NXP Semiconductors, LPC2926_27_29 Datasheet - Page 58

• Manufacturer Part Number: LPC2926_27_29
• Description: The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2926_27_29
Product data sheet
Table 32.
Legend:
‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored
‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored
‘+’ Indicates that the related register bit is readable and writable
Branch clock name
CLK_SAFE
CLK_SYS_CPU
CLK_SYS
CLK_SYS_PCR
CLK_SYS_FMC
CLK_SYS_RAM0
CLK_SYS_RAM1
CLK_SYS_SMC
CLK_SYS_GESS
CLK_SYS_VIC
CLK_SYS_PESS
CLK_SYS_GPIO0
CLK_SYS_GPIO1
CLK_SYS_GPIO2
CLK_SYS_GPIO3
CLK_SYS_IVNSS_A
CLK_SYS_MSCSS_A
CLK_SYS_DMA
CLK_SYS_USB
CLK_PCR_SLOW
CLK_IVNSS_APB
CLK_IVNSS_CANC0
CLK_IVNSS_CANC1
CLK_IVNSS_I2C0
CLK_IVNSS_I2C1
CLK_IVNSS_LIN0
CLK_IVNSS_LIN1
CLK_MSCSS_APB
CLK_MSCSS_MTMR0
CLK_MSCSS_MTMR1
CLK_MSCSS_PWM0
CLK_MSCSS_PWM1
CLK_MSCSS_PWM2
CLK_MSCSS_PWM3
CLK_MSCSS_ADC0_APB BASE_MSCSS_CLK
CLK_MSCSS_ADC1_APB BASE_MSCSS_CLK
Branch clock overview
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 28 September 2010
Base clock
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_PCR_CLK
BASE_IVNSS_CLK
BASE_IVNSS_CLK
BASE_IVNSS_CLK
BASE_IVNSS_CLK
BASE_IVNSS_CLK
BASE_IVNSS_CLK
BASE_IVNSS_CLK
BASE_MSCSS_CLK
BASE_SAFE_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_SYS_CLK
BASE_MSCSS_CLK
BASE_MSCSS_CLK
BASE_MSCSS_CLK
BASE_MSCSS_CLK
BASE_MSCSS_CLK
BASE_MSCSS_CLK
ARM9 microcontroller with CAN, LIN, and USB
LPC2926/2927/2929
Implemented switch on/off
mechanism
WAKE-UP
0
+
+
+
+
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+
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+
+
+
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+
+
+
+
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+
+
+
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+
+
+
+
AUTO
0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
© NXP B.V. 2010. All rights reserved.
1
1
1
+
+
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+
+
+
+
+
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+
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1
+
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RUN
1
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