LPC2926_27_29 NXP Semiconductors, LPC2926_27_29 Datasheet - Page 45

• Manufacturer Part Number: LPC2926_27_29
• Description: The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2926_27_29
Product data sheet
Fig 10. PWM block diagram
APB system bus
IRQ capt_match
6.15.5.2 Synchronizing the PWM counters
IRQ pwm
The PWM block diagram in
functionality is split into two major parts, a APB domain and a PWM domain, both of which
run on clocks derived from the BASE_MSCSS_CLK. This split into two domains affects
behavior from a system-level perspective. The actual PWM and prescale counters are
located in the PWM domain but system control takes place in the APB domain.
The actual PWM consists of two counters; a 16-bit prescale counter and a 16-bit PWM
counter. The position of the rising and falling edges of the PWM outputs can be
programmed individually. The prescale counter allows high system bus frequencies to be
scaled down to lower PWM periods. Registers are available to capture the PWM counter
values on external events.
Note that in the Modulation and Sampling SubSystem, each PWM has its individual clock
source CLK_MSCSS_PWMx (x runs from 0 to 3). Both the prescale and the timer
counters within each PWM run on this clock CLK_MSCSS_PWMx, and all time references
are related to the period of this clock. See
these clocks.
A mechanism is included to synchronize the PWM period to other PWMs by providing a
sync input and a sync output with programmable delay. Several PWMs can be
synchronized using the trans_enable_in/trans_enable_out and sync_in/sync_out ports.
See
LPC2926/2927/2929. PWM 0 can be master over PWM 1; PWM 1 can be master over
PWM 2, etc.
Figure 8
REGISTERS
CONTROL
PWM
&
for details of the connections of the PWM modules within the MSCSS in the
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 28 September 2010
PWM counter value
capture data
config data
APB DOMAIN
update
Figure 10
IRQs
shows the basic architecture of each PWM. PWM
ARM9 microcontroller with CAN, LIN, and USB
PWM DOMAIN
Section 6.16
LPC2926/2927/2929
sync_out
sync_in
REGISTERS
PRESCALE
COUNTER,
COUNTER
SHADOW
PWM,
for information on generation of
transfer_enable_in
transfer_enable_out
&
© NXP B.V. 2010. All rights reserved.
match outputs
capture inputs
trap input
carrier inputs
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