ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 126

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

Digital Signal Processing Block
Figure 4–34. Simple Multiplier Mode
Note to
(1)
4–60
Stratix GX Device Handbook, Volume 1
Data B
Data A
These signals are not registered or registered once to match the data path pipeline.
Figure
shiftout B
4–34:
shiftin B
shiftout A
ENA
ENA
D
D
CLRN
CLRN
DSP blocks can also implement one 36
mode. DSP blocks use four 18
dedicated adder and internal shift circuitry to achieve 36-bit
multiplication. The input shift register feature is not available for the
36
that is normally a multiplier-result-output register as a pipeline stage for
the 36
mode.
shiftin A
signa (1)
signb (1)
×
Q
Q
clock
36-bit multiplier. In 36
ena
aclr
×
36-bit multiplier.
ENA
D
Figure 4–35
CLRN
×
36-bit mode, the device can use the register
Q
×
18-bit multipliers combined with
shows the 36
×
36-bit multiplier in multiplier
ENA
D
CLRN
Q
×
36-bit multiply
Altera Corporation
February 2005
Data Out