ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 155

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

Figure 4–55. External Clock Outputs for Enhanced PLLs 11 & 12
Note to
(1)
Altera Corporation
February 2005
Counter
SSTL-3 class I
SSTL-3 class II
AGP (1× and 2× )
CTT
Table 4–19. I/O Standards Supported for Enhanced PLL Pins (Part 2 of 2)
g 0
For PLL 11, this pin is CLK13n; for PLL 12 this pin is CLK7n.
Figure
From Internal
I/O Standard
Logic or IOE
4–55:
Enhanced PLLs 11 and 12 support one single-ended output each (see
Figure
Therefore, to minimize jitter, do not place switching I/O pins next to this
output pin.
Stratix GX devices can drive any enhanced PLL driven through the global
clock or regional clock network to any general I/O pin as an external
output clock. The jitter on the output clock is not guaranteed for these
cases.
Clock Feedback
The following four feedback modes in Stratix GX device enhanced PLLs
allow multiplication and/or phase and delay shifting:
■
■
Zero delay buffer: The external clock output pin is phase-aligned
with the clock input pin for zero delay.
External feedback: The external feedback input pin, FBIN, is
phase-aligned with the clock input, CLK, pin. Aligning these clocks
allows you to remove clock delay and skew between devices. This
mode is only possible for PLLs 5 and 6. PLLs 5 and 6 each support
INCLK
4–55). These outputs do not have their own VCC and GND signals.
v
v
v
v
Input
FBIN
v
v
v
v
Stratix GX Device Handbook, Volume 1
PLLENABLE
or CLK6n, I/O, PLL12_OUT (1)
CLK13n, I/O, PLL11_OUT
Stratix GX Architecture
EXTCLK
Output
v
v
v
v
4–89