ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 207

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
June 2006
Reference Clock
Jitter
tolerance
(peak-to-
peak)
Reference
input clock
frequency
Serial data
rate
(general)
Serial data
rate (8B/10B
encoded)
Parallel
transceiver/
logic array
interface
speed
Rate
matching
frequency
tolerance
8B/10B Custom Receiver Jitter Tolerance using Encoded CJPAT
Deterministic
jitter
Total jitter
Fibre Channel Receiver Jitter Tolerance using 8B/10B Encoded CJTPAT
Deterministic
jitter
Total jitter
Description
Receiver
Table 6–7. Stratix GX Transceiver Block AC Specification (Part 2 of 7)
Symbol /
Jitter
components
<20 MHz
Wideband
Dedicated
refclkb
PLD clock
resources
Commercial /
industrial
Commercial /
industrial
XAUI mode only
500 Mbps
500 Mbps
1.0625 Gbps
1.0625 Gbps
Conditions
pins
Min
614
500
25
25
20
Speed Grade
-5 Commercial
Typ
3,187.5
3,187.5
398.4
±100
Max
0.45
0.71
0.37
0.68
650
325
20
50
(1)
Min
614
500
25
25
20
-6 Commercial &
Industrial Speed
Typ
Grade
(1)
Stratix GX Device Handbook, Volume 1
Note (2)
3,187.5
3,187.5
±100
Max
0.45
0.71
0.37
0.68
650
325
375
20
50
DC & Switching Characteristics
Note (2)
Min
614
500
25
25
20
-7 Commercial &
Industrial Speed
Grade
Typ
(1)
156.25
312.5
2,500
2,500
312.5
±100
Max
0.45
0.71
0.37
0.68
20
50
Mbps
Mbps
MHz
MHz
MHz
ppm
Unit
ps
ps
UI
UI
UI
UI
6–5