ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 136

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

PLLs & Clock Networks
4–70
Stratix GX Device Handbook, Volume 1
Figure 4–41. Global Clock Resources
Regional Clock Network
There are four regional clock networks RCLK[3..0] within each
quadrant of the Stratix GX device that are driven by the same dedicated
CLK[7..0] and CLK[15..12] input pins, PLL outputs, or transceiver
clocks. The regional clock networks only pertain to the quadrant they
drive into. The regional clock networks provide the lowest clock delay
and skew for logic contained within a single quadrant. The CLK clock pins
symmetrically drive the RCLK networks within a particular quadrant, as
shown in
CLK[3..0]
Figure
4–42.
CLK[7..4]
Global Clock [15..0]
CLK[15..12]
Altera Corporation
February 2005
Transceiver
Clocks