ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 181

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
February 2005
Notes to
(1)
(2)
SSTL-3 class I and II
AGP (1
CTT
Table 4–27. Stratix GX Supported I/O Standards (Part 2 of 2)
This I/O standard is only available on input and output clock pins.
This I/O standard is only available on output column clock pins.
I/O Standard
×
Table
and 2
×
4–27:
)
f
Voltage-referenced
Voltage-referenced
Voltage-referenced
For more information on I/O standards supported by Stratix GX
devices, see the Selectable I/O Standards in Stratix & Stratix GX Devices
chapter of the Stratix GX Device Handbook, Volume 2.
Stratix GX devices contain eight I/O banks in addition to the four
enhanced PLL external clock out banks, as shown in
I/O banks on the right and left of the device contain circuitry to support
high-speed differential I/O for LVDS, LVPECL, 3.3-V PCML, and
HyperTransport inputs and outputs. These banks support all I/O
standards listed in
SSTL-18 Class II, and HSTL Class II outputs. The top and bottom I/O
banks support all single-ended I/O standards. Additionally, Stratix GX
devices support four enhanced PLL external clock output banks,
allowing clock output capabilities such as differential support for SSTL
and HSTL.
Type
Table 4–28
Table 4–27
Input Reference
Voltage (V
shows I/O standard support for each I/O bank.
1.32
(V)
1.5
1.5
except PCI I/O pins or PCI-X 1.0, GTL,
REF
)
Stratix GX Device Handbook, Volume 1
Voltage (V
Output Supply
(V)
3.3
3.3
3.3
CCIO
Stratix GX Architecture
Figure
)
Voltage (V
Termination
4–69. The four
Board
N/A
(V)
1.5
1.5
4–115
TT
)