ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 256

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

Timing Model
6–54
Stratix GX Device Handbook, Volume 1
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
Differential HSTL
LVDS
LVPECL
PCML
HyperTransport technology
Table 6–81. Stratix GX Maximum Input Clock Rate for CLK[7..4] & CLK[15..12] Pins
I/O Standard
Maximum Input & Output Clock Rates
Tables 6–81
and row pins in Stratix GX devices.
through
-5 Speed Grade -6 Speed Grade -7 Speed Grade
422
422
400
400
400
400
422
422
400
645
300
422
422
422
300
300
400
400
400
400
400
400
422
422
422
300
645
500
6–83
show the maximum input clock rate for column
422
422
422
422
422
250
250
350
350
350
350
350
350
350
350
350
350
422
422
422
422
422
250
350
645
645
275
500
390
390
390
390
390
200
200
300
300
300
300
300
300
300
300
300
300
390
390
390
390
390
200
300
622
622
275
450
Altera Corporation
June 2006
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit