ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 139

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ep1sgx25d

Manufacturer Part Number
ep1sgx25d
Description
Stratix Gx Device Family Data Sheet
Manufacturer
Altera Corporation
Datasheet

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Altera Corporation
February 2005
Figure 4–44. EP1SGX40 Device Fast Regional Clock Pin Connections to Fast
Regional Clocks
Combined Resources
Within each region, there are 22 distinct dedicated clocking resources
consisting of 16 global clock lines, 4 regional clock lines, and 2 fast
regional clock lines. Multiplexers are used with these clocks to form 8-bit
busses to drive LAB row clocks, column IOE clocks, or row IOE clocks.
Another multiplexer at the LAB level selects two of the eight row clocks
to feed the LE registers within the LAB. See
fclk[1..0]
Fast Clock
Fast Clock
[3]
[4]
Fast Clock
Fast Clock
Stratix GX Device Handbook, Volume 1
[2]
[5]
Fast Clock
Fast Clock
Figure
[1]
[6]
Stratix GX Architecture
4–45.
Fast Clock
Fast Clock
[0]
[7]
4–73

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