ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 153

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

Altera Corporation
February 2005
External Clock Outputs
Enhanced PLLs 5 and 6 each support up to eight single-ended clock
outputs (or four differential pairs). See
Figure 4–54. External Clock Outputs for PLLs 5 & 6
Notes to
(1)
(2)
Any of the four external output counters can drive the single-ended or
differential clock outputs for PLLs 5 and 6. This means one counter or
frequency can drive all output pins available from PLL 5 or PLL 6. Each
e 0 Counter
e 1 Counter
e 2 Counter
e 3 Counter
Each external clock output pin can be used as a general purpose output pin from
the logic array. These pins are multiplexed with IOE outputs.
Two single-ended outputs are possible per output counter—either two outputs of
the same frequency and phase or one shifted 180°.
Figure
4–54:
4
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
From IOE (1)
Stratix GX Device Handbook, Volume 1
(2)
Figure
4–54.
Stratix GX Architecture
extclk0_a
extclk0_b
extclk1_a
extclk1_b
extclk2_a
extclk2_b
extclk3_a
extclk3_b
4–87