ep1sgx25d Altera Corporation, ep1sgx25d Datasheet - Page 176

• Manufacturer Part Number: ep1sgx25d
• Description: Stratix Gx Device Family Data Sheet
• Manufacturer: Altera Corporation

I/O Structure
Figure 4–68. Simplified Diagram of the DQS Phase-Shift Circuitry
4–110
Stratix GX Device Handbook, Volume 1
Reference
Clock
Input
See the External Memory Interfaces chapter of the Stratix GX Device
Handbook, Volume 2 for more information on external memory interfaces.
Programmable Drive Strength
The output buffer for each Stratix GX device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL and
LVCMOS standard has several levels of drive strength that the user can
control. SSTL-3 class I and II, SSTL-2 class I and II, HSTL class I and II, and
3.3-V GTL+ support a minimum setting, the lowest drive strength that
guarantees the I
provides signal slew rate control to reduce system noise and signal
overshoot.
Comparator
Phase
Delay Chains
OH
/I
OL
of the standard. Using minimum settings
Up/Down
Counter
6
Control Signals
to DQS Pins
Altera Corporation
February 2005