tmp88cs38ng TOSHIBA Semiconductor CORPORATION, tmp88cs38ng Datasheet - Page 30

• Manufacturer Part Number: tmp88cs38ng
• Description: Cmos 8-bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

1.5.2
1.5.3
(3) Interrupt return
Software Interrupt (INTSW)
interrupt processing (INTSW is highest prioritized interrupt). However, if processing of a
non-maskable interrupt is already underway, executing the SWI instruction will not
generate a software interrupt but will result in the same operation as the [NOP]
instruction.
1.
2.
External Interrupts
INT3, INT4, and
(Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also
possible with INT2, INT3 and INT4.
input/output port, and is configured as an input port during reset.
selection are performed by the external interrupt control register (EINTCR). Edge selecting
and noise rejection control for INT3 pin input are preformed by the remote control signal
preprocessor control registers. (Refer to the section of the remote control signal
preprocessor.) When INT0EN = 0, the IL3 will not be set even if the falling edge of
pin input is detected.
Executing the [SWI] instruction generates a software interrupt and immediately starts
Use the [SWI] instruction only for detection of the address error or for debugging.
The TMP88CS38/CM38A/CP38A each have five external interrupt inputs (
The
Edge selection, noise rejection control except INT3 pin input and
executed. Thus, the next interrupt can be accepted immediately after the interrupt
return instruction is executed.
Address error detection
from a non-existent memory address. Code FF
interrupt is generated and an address error is detected. The address error detection
range can be further expanded by writing FF
Address-trap reset is generated in case that an instruction is fetched from RAM, SFR
or DBR areas.
Debugging
break point setting address.
Note: When the interrupt processing time is longer than the interrupt request generation
1. The contents of the program counter and
2. The stack pointer is incremented 5 times. 2. The stack pointer is incremented 5 times.
3. The interrupt master enable flag is set to
4. The interrupt nesting counter is
[RETI] Maskable Interrupt Return
The interrupt return instructions [RETI]/[RETN] perform the following operations.
Interrupt requests are sampled during the final cycle of the instruction being
FF
Debugging efficiency can be increased by placing the SWI instruction at the software
INT0
the program status word are restored
from the stack.
“1”.
decremented, and the interrupt nesting
flag is changed.
H
is read if for some cause such as noise the CPU attempts to fetch an instruction
time, the interrupt service task is performed but not the main task.
/P50 pin can be configured as either an external interrupt input pin or an
INT5
). Three of these are equipped with digital noise rejection circuits
88CS38-30
1. The contents of the program counter and program status
3. The interrupt master enable flag is set to “1” only when a
4. The interrupt nesting counter is decremented, and the
word are restored from the stack.
non-maskable interrupt is accepted in interrupt enable status.
However, the interrupt master enable flag remains at “0”
when so clear by an interrupt service program.
interrupt nesting flag is changed.
[RETN] Non-maskable Interrupt Return
H
to unused areas of the program memory.
H
is the SWI instruction, so a software
TMP88CS38/CM38A/CP38A
INT0
/P50 pin function
INT0
2007-09-12
, INT2,
INT0