tmp88cs38ng TOSHIBA Semiconductor CORPORATION, tmp88cs38ng Datasheet - Page 97

• Manufacturer Part Number: tmp88cs38ng
• Description: Cmos 8-bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

PIN
INTSBI
interrupt
request
SCL pin
SDA pin
2.9.8
Data Transfer of I
(1) Device initialization
(2) Start condition and slave address generation
Specify the data length to 8 bits to count clocks for an acknowledge signal. Set a
transfer frequency to the SCK in SBICRA.
addressing format.
default setting to a slave receiver mode, clear “0” to the MST, TRX and BB in SBICRB,
set “1” to the PIN, “10” to the SBIM, and “00” to bits SWRST1 and SWRST0.
the SBIDBR.
bus and then, the slave address and the direction bit which are set to the SBIDBR are
output. An INTSBI interrupt request occurs at the 9th falling edge of a SCL clock cycle,
and the PIN is cleared to “0”. The SCL pin is pulled down to the low level while the PIN
is “0”. When an interrupt request occurs the TRX changes by the hardware according
to the direction bits only when an acknowledge signal is returned from the slave device.
Note: The initialization of a serial bus interface circuit must be complete within the time
Note 1: Do not write a slave address to be output to the SBIDBR while data is transferred. If
Note 2: The bus free must be confirmed by software within 98.0 μs (the shortest
Figure 2.9.13 Start Condition Generation and Slave Address Transfer
Start condition
For initialization of device, set the ACK in SBICRA to “1” and the BC to “000”.
Next, set the slave address to the SA in I2CAR and clear the ALS to “0” to set an
After confirming that the serial bus interface pin is high-level, for specifying the
Confirm a bus free status (when BB = 0).
Set the ACK to “1” and specify a slave address and a direction bit to be transmitted to
By writing “1” to the MST, TRX, BB and PIN, the start condition is generated on a
from all devices which are connected to a bus have initialized to and device does
not generate a start condition. If not, the data can not be received correctly because
the other device starts transferring before an end of the initialization of a serial bus
interface circuit.
data is written to the SBIDBR, data to been outputting may be destroyed.
transmitting time according to the I
address to be output. Only when the bus free is confirmed, set “1” to the MST, TRX,
BB, and PIN doesn’t finish within 98.0 μs, the other masters may start the
transferring and the slave address data written in SBIDBR may be broken.
A6
1
2
C Bus
A5
2
A4
Slave address + direction bit
3
88CS38-97
A3
4
A2
5
2
C bus standard) after setting of the slave
A1
6
A0
7
TMP88CS38/CM38A/CP38A
R/
W
8
9
Acknowledge
signal from a
slave device
2007-09-12