tmp88cs38ng TOSHIBA Semiconductor CORPORATION, tmp88cs38ng Datasheet - Page 93

• Manufacturer Part Number: tmp88cs38ng
• Description: Cmos 8-bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(4) Slave address and address recognition mode specification
(5) Master/slave selection
(6) Transmitter/receiver selection
Mode
Master
Slave
mode
mode
the slave address, clear the ALS (Bit0 in I2CAR) to “0”, and set the SA (Bits 7 to 1 in
I2CAR) to the slave address.
the slave address, set the ALS to “1”. With a free data format, the slave address and the
direction bit are not recognized, and they are processed as data from immediately after
start condition.
device, the MST should be cleared to “0”.
cleared to “0” by the hardware.
set the device as a receiver, the TRX should be cleared to “0”. When data with an
addressing format is transferred in the slave mode, the TRX is set to “1” by a hardware
if the direction bit (R/
hardware if the bit is “0. In the master mode, after an acknowledge signal is returned
from the slave device, the TRX is cleared to “0” by a hardware if a transmitted direction
bit is “1”, and is set to “1” by a hardware if it is “0”. When an acknowledge signal is not
returned, the current condition is maintained.
cleared to “0” by the hardware. The following table show TRX changing conditions in
each mode and TRX value after changing.
and a direction bit are not recognized. They are handled as data just after generating a
start condition. The TRX is not changed by a hardware.
When the serial bus interface circuit is used with an addressing format to recognize
When the serial bus interfac circuit is used with a free data format not to recognize
To set a master device, the MST (Bit7 in SBICRB) should be set to “1”. To set a slave
When a stop condition on the bus or an arbitration lost is detected, the MST is
To set the device as a transmitter, the TRX (Bit6 in SBICRB) should be set to “1”. To
When a stop condition on the bus or an arbitration lost is detected, the TRX is
When a serial bus interface circuit operates in the free data format, a slave address
the bus becomes the low level. After detecting this situation, master 2 resets
counting a clock pulse in the high level and sets the SCL pin to the low level.
SCL pin to the high level. Since master 2 holds the SCL line of the bus at the low
level, master 1 waits for counting a clock pulse in the high level. After master 2
sets a clock pulse to the high level at point “c” and detects the SCL line of the bus
at the high level, master 1 starts counting a clock pulse in the high level. Then,
the master, which has finished the counting a clock pulse in the high level, pulls
down the SCL pin to the low level.
high-level period and the master device with the longest low-level period from
among those master devices connected to the bus.
As master 1 pulls down the SCL pin to the low level at point “a”, the SCL line of
Master 1 finishes counting a clock pulse in the low level at point “b” and sets the
The clock pulse on the bus is deteminded by the master device with the shortest
Direction Bit
“0”
“1”
“0”
“1”
W
) sent from the master device is “1”, and is cleared to “0” by a
88CS38-93
A received slave address is the
same value set to I2CAR
ACK signal is returned
Conditions
TMP88CS38/CM38A/CP38A
TRX after Changing
“0”
“1”
“1”
“0”
2007-09-12