hm5264165f-75 Elpida Memory, Inc., hm5264165f-75 Datasheet
hm5264165f-75
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hm5264165f-75 Summary of contents
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... HM5264165F-75/A60/B60 HM5264805F-75/A60/B60 HM5264405F-75/A60/B60 64M LVTTL interface SDRAM 1-Mword 16-bit 4-bank/2-Mword /4-Mword Description The HM5264165F is a 64-Mbit SDRAM organized as 1048576-word is a 64-Mbit SDRAM organized as 2097152-word organized as 4194304-word 4-bit clock input packaged in standard 54-pin plastic TSOP II. Features 3.3 V power supply ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Programmable CAS latency: 2/3 Byte control by DQM: DQM (HM5264805F/HM5264405F) DQMU/DQML (HM5264165F) Refresh cycles: 4096 refresh cycles/ variations of refresh Auto refresh Self refresh Full page burst length capability Sequential burst Burst stop capability Ordering Information Type No. Frequency 1 HM5264165FTT-75* 133 MHz ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Arrangement (HM5264165F) Pin Description Pin name Function A0 to A13 Address input Row address Column address Bank select address A12/A13 (BS) CKE DQ0 to DQ15 Data-input/output CS Chip select RAS Row address strobe command CAS Column address strobe command Data Sheet E0135H10 ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Arrangement (HM5264805F) Pin Description Pin name Function A0 to A13 Address input Row address Column address Bank select address A12/A13 (BS) CKE DQ0 to DQ7 Data-input/output CS Chip select RAS Row address strobe command CAS Column address strobe command Data Sheet E0135H10 ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Arrangement (HM5264405F) Pin Description Pin name Function A0 to A13 Address input Row address Column address Bank select address A12/A13 (BS) CKE DQ0 to DQ3 Data-input/output CS Chip select RAS Row address strobe command CAS Column address strobe command Data Sheet E0135H10 ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Block Diagram (HM5264165F Column address counter Row decoder Memory array Bank 0 4096 row X 256 column X 16 bit Data Sheet E0135H10 A13 Column address Row address buffer buffer Row decoder Row decoder Memory array Memory array Bank 1 Bank 2 ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Block Diagram (HM5264805F Column address counter Row decoder Memory array Bank 0 4096 row X 512 column X 8 bit Data Sheet E0135H10 A0 to A13 Column address Row address buffer buffer Row decoder Row decoder Memory array Memory array Bank 1 Bank 2 ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Block Diagram (HM5264405F Column address counter Row decoder Memory array Bank 0 4096 row X 1024 column X 4 bit Data Sheet E0135H10 A13 Column address Row address buffer buffer Row decoder Row decoder Memory array Memory array Bank 1 Bank 2 ...
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... Write operation: If DQM, DQMU/DQML is High, the previous data is held (the new data is not written). If DQM, DQMU/DQML is Low, the data is written. (The latency of DQM, DQMU/DQML during writing is 0 clock.) DQ0 to DQ15 (DQ pins): Data is input to and output from these pins (DQ0 to DQ15; HM5264165F, DQ0 to DQ7; HM5264805F, DQ0 to DQ3; HM5264405F). V and V Q (power supply pins): 3 ...
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... No operation [NOP]: This command is not an execution command. However, the internal operations continue. Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page (256; HM5264165F, 512; HM5264805F, 1024; HM5264405F)), and is illegal otherwise. When data input/output is completed for a full page of data, it automatically returns to the start address, and input/output is performed repeatedly. ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (BS). After the read operation, the output buffer becomes High-Z ...
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... DOD The SDRAM can mask input/output data by means of DQM, DQMU/DQML. DQMU masks the upper byte and DQML masks the lower byte. (HM5264165F) During reading, the output buffer is set to Low-Z by setting DQM, DQMU/DQML to Low, enabling data output. On the other hand, when DQM, DQMU/DQML is set to High, the output buffer becomes High-Z, disabling data output ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 CKE Truth Table Current state Command Active Clock suspend mode entry Any Clock suspend Clock suspend Clock suspend mode exit Idle Auto-refresh command (REF) Idle Self-refresh entry (SELF) Idle Power down entry Self refresh Self refresh exit (SELFX) Power down ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Self-refresh entry [SELF]: When this command is input during the IDLE state, the SDRAM starts self- refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self- refresh is performed internally and automatically, external refresh operations are unnecessary. ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 CS RAS CAS WE Current state Row active Read Read with auto- H precharge ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 CS RAS CAS WE Current state Write Write with auto- H precharge Refresh (auto- H refresh ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 From PRECHARGE state, command operation To [DESL], [NOP] or [BST]: When these commands are executed, the SDRAM enters the IDLE state after t has elapsed from the completion of precharge. RP From IDLE state, command operation To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation. ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 From READ with AUTO-PRECHARGE state, command operation To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the SDRAM then enters precharge mode. To [ACTV]: This command makes other banks bank active. (However, an interval of t Attempting to make the currently active bank active results in an illegal command. ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Simplified State Diagram MODE REGISTER SET (on full page) Write CKE_ WRITE SUSPEND CKE WRITE WITH AP CKE_ WRITEA SUSPEND CKE POWER POWER APPLIED ON Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Mode Register Configuration The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. A13, A12, A11, A10, A9, A8: (OPCODE): The SDRAM has two types of write modes. One is the burst write mode, and the other is the single write mode ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Burst Sequence Burst length = 2 Starting Ad. Addressing(decimal) A0 Sequential Burst length = 8 Starting Ad. Addressing(decimal Sequential ...
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... Latency - 1) cycle after read command set. HM5264165F, HM5264805F series, HM5264405F can perform a burst read operation. The burst length can be set full-page (256; HM5264165F, 512; HM5264805F, 1024; HM5264405F). The start address for a burst read is specified by the column address (AY0 to AY7; ...
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... The burst length can be set and full-page, like burst read operations. The write start address is specified by the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (A12/A13) at the write command set cycle. ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0 single write operation, data is only written to the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (A12/A13) specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0 clock). ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write with auto-precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Full-page Burst Stop Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read. The timing from command input to the last data changes depending on the CAS latency setting. In addition, the BST command is valid only during full-page burst mode, and is illegal with burst lengths and 8 ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Burst stop command at burst write: The burst stop command (BST command) is used to stop data input during a full-page burst write. No data is written in the same clock as the BST command, and in subsequent clocks. In addition, the BST command is only valid during full-page burst mode, and is illegal with burst lengths and 8 ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Command Intervals Read command to Read command interval: 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write command to Write command interval: 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. In the case of burst writes, the second write command has priority. ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read command to Write command interval: 1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write command to Read command interval: 1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is valid ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read with auto precharge to Write command interval 1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input. The internal auto-precharge of one bank starts at the next clock of the second command. ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. However, in case of a burst write, data will continue to be written until one clock before the read command is executed ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the clocks defined by l interrupted, if the precharge command is input during burst read ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 READ to PRECHARGE Command Interval (same bank): To stop output data CAS Latency = 2, Burst Length = full page burst CLK READ Command PRE/PALL Dout CAS Latency = 3, Burst Length = full page burst CLK READ PRE/PALL Command Dout Data Sheet E0135H10 ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data must be masked by means of ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Bank active command interval: 1. Same bank: The interval between the two bank-active commands must be no less than the case of different bank-active commands: The interval between the two bank-active commands must be no less than t . RRD Bank Active to Bank Active for Same Bank ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Mode register set to Bank-active command interval: The interval between setting the mode register and executing a bank-active command must be no less than l CLK Command MRS Address CODE Mode Register Set Data Sheet E0135H10 . RSA ACTV BS & ROW I RSA Bank Active ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DQM Control The DQM mask the DQ data. The DQMU and DQML mask the upper and lower bytes of the DQ data, respectively. The timing of DQMU/DQML is different during reading and writing. Reading: When data is read, the output buffer can be controlled by DQM, DQMU/DQML. By setting DQM, DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Refresh Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the auto- refresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 4096 cycles/64 ms ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Power up sequence CKE, DQM, Low DQMU/DQML Low CLK Low CS, DQ Power stabilize Absolute Maximum Ratings Parameter Voltage on any pin relative Supply voltage relative Short circuit output current Power dissipation Operating temperature Storage temperature Note: 1 ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 V /V Clamp IL IH clamp for CLK, CKE, CS, DQM and D/Q pins. This SDRAM has V and Minimum V Clamp Current IL V (V) IL –2 –1.8 –1.6 –1.4 –1.2 –1 –0.9 –0.8 –0.6 –0.4 –0 –2 –5 –10 –15 –20 –25 –30 – ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Minimum V Clamp Current Data Sheet E0135H10 44 I (mA 5.5 3.5 1 ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 I /I Characteristics OL OH Output Low Current ( Vout (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3 3.45 250 200 150 100 0.5 Data Sheet E0135H10 Min (mA) Max (mA 108 51 134 58 151 70 188 72 194 75 203 77 209 77 212 80 220 81 223 1 1.5 2 2.5 Vout (V) OL min max 3 3 ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Output High Current ( +70˚ Vout (V) 3.45 3.3 3 2.6 2.4 2 1.8 1.65 1.5 1 0.5 1 –100 –200 –300 –400 –500 –600 Data Sheet E0135H10 3 3. Min (mA) Max (mA) — –3 — –28 0 –75 –21 –130 –34 –154 –59 – ...
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... Input leakage current I LI Output leakage current I LO Output high voltage V OH Output low voltage V OL Data Sheet E0135H10 , 3.3 V ± 0 HM5264165F -75 -A60 -B60 Max Min Max Min Max Unit Test conditions — 65 — 65 — 65 — 65 — 65 — 65 — ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DC Characteristics ( +70˚C, V (HM5264805F) Parameter Symbol Min Operating current (CAS latency = 2) I CC1 (CAS latency = 3) I CC1 Standby current in power down I CC2P Standby current in power down I CC2PS (input signal stable) Standby current in non power I CC2N down Standby current in non power ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DC Characteristics ( +70˚C, V (HM5264405F) Parameter Symbol Min Operating current (CAS latency = 2) I CC1 (CAS latency = 3) I CC1 Standby current in power down I CC2P Standby current in power down I CC2PS (input signal stable) Standby current in non power I CC2N down Standby current in non power ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Notes depends on output load condition when the device is selected output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. ...
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... DPL precharge lead time Active (a) to Active (b) t RRD command period Transition time (rise and fall Refresh period t REF Data Sheet E0135H10 , 3.3 V ± 0 HM5264165F/HM5264805F/HM5264405F -75 -A60 PC/100 Symbol Min Max Min Max Tclk 10 — 10 — Tclk 7.5 — 10 — ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Notes measurement assumes t 2. Access time is measured at 1.5 V. Load condition pF (min) defines the time at which the outputs achieves the low impedance state (max) defines the time at which the outputs achieves the high impedance state. ...
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... Last data out to precharge (early precharge) (CAS latency = 2) (CAS latency = 3) Column command to column command Write command to data in latency DQM to data in DQM to data out CKE to CLK disable Register set to active command Data Sheet E0135H10 HM5264165F/ HM5264805F/ HM5264405F -75 133 PC/100 Symbol Symbol 7 ...
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... Burst stop to write data ignore Notes are recommended value. RCD RRD 2. Be valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP]. Data Sheet E0135H10 54 HM5264165F/ HM5264805F/ HM5264405F -75 133 PC/100 Symbol Symbol 7 CDD ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Timing Waveforms Read Cycle CKH CKL CLK V IH CKE t RCD RAS CAS A10 Address t CS ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write Cycle CKH CKL CLK V IH CKE t RCD RAS CAS A10 Address t CS DQM, DQMU/DQML ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Mode Register Set Cycle CLK V CKE IH CS RAS CAS WE BS Address valid code DQM, DQMU/DQML DQ (output) DQ (input) l RSA l RP Precharge Mode If needed register Set Read Cycle/Write Cycle CLK V CKE IH CS RAS CAS WE BS Address ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read/Single Write Cycle CLK V CKE IH CS RAS CAS WE BS Address R:a C:a DQM, DQMU/DQML DQ (input) DQ (output) Bank 0 Bank 0 Active Read CKE RAS CAS WE BS R:a C:a Address DQM, DQMU/DQML DQ (input) DQ (output) Bank 0 Bank 0 Active Read Data Sheet E0135H10 ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read/Burst Write Cycle CLK CKE CS RAS CAS WE BS Address R:a C:a DQM, DQMU/DQML DQ (input) DQ (output) Bank 0 Bank 0 Active Read V CKE IH CS RAS CAS WE BS R:a C:a Address DQM, DQMU/DQML DQ (input) DQ (output) Bank 0 Bank 0 Active Read Data Sheet E0135H10 ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Full Page Read/Write Cycle CLK V CKE IH CS RAS CAS WE BS Address R:a C:a R:b DQM, DQMU/DQML DQ (output) DQ (input) Bank 0 Bank 0 Bank 3 Active Read Active V CKE IH CS RAS CAS WE BS Address R:a C:a R:b DQM, DQMU/DQML DQ (output) DQ (input) a a+1 a+2 Bank 0 Bank 0 Bank 3 Active Write Active Data Sheet E0135H10 ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Auto Refresh Cycle CLK CKE RAS CAS WE BS Address A10=1 DQM, DQMU/DQML DQ (input) DQ (output Auto Refresh Precharge If needed Self Refresh Cycle CLK CKE Low CKE CS RAS CAS WE BS Address A10=1 DQM, DQMU/DQML DQ (input) DQ (output ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Clock Suspend Mode t CES CLK CKE CS RAS CAS WE BS Address R:a DQM, DQMU/DQML DQ (output) DQ (input) Bank0 Active clock Active clock Active suspend start suspend end CKE CS RAS CAS WE BS Address R:a DQM, DQMU/DQML DQ (output) DQ (input) Bank0 Active clock ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Power Down Mode CLK CKE CS RAS CAS WE BS Address A10=1 DQM, DQMU/DQML DQ (input) DQ (output Precharge command If needed Initialization Sequence CLK CKE RAS CAS WE Address valid DQM DQMU/DQML All banks Auto Refresh Precharge Data Sheet E0135H10 ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Package Dimensions HM5264165FTT/FLTT HM5264805FTT/FLTT HM5264405FTT/FLTT Series (TTP-54D) 22.22 22.72 Max 54 1 0.80 +0.10 *0.30 –0.05 0.13 M 0.28 0.05 0.91 Max 0.10 *Dimension including the plating thickness Base material dimension Data Sheet E0135H10 11.76 0.20 0 – 5 0.50 Hitachi Code JEDEC EIAJ Mass (reference value) Unit: mm 0.80 0.10 TTP-54D — — 0.53 g ...
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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Cautions 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document ...