hm5264165f-75 Elpida Memory, Inc., hm5264165f-75 Datasheet - Page 20

• Manufacturer Part Number: hm5264165f-75
• Description: 64m Lvttl Interface Sdram
• Manufacturer: Elpida Memory, Inc.

HM5264165F/HM5264805F/HM5264405F-75/A60/B60
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The
mode register consists of five sections, each of which is assigned to address pins.
A13, A12, A11, A10, A9, A8: (OPCODE): The SDRAM has two types of write modes. One is the burst
write mode, and the other is the single write mode. These bits specify write mode.
Burst read and burst write: Burst write is performed for the specified burst length starting from the column
address specified in the write cycle.
Burst read and single write: Data is only written to the column address specified during the write cycle,
regardless of the burst length.
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the CAS latency.
A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected.
A2, A1, A0: (BL): These pins specify the burst length.
20
A13
A13
X
X
X
0
A12
A12
0
X
X
X
A11
X
X
X
0
A11 A10
OPCODE
A10
X
X
X
0
A6 A5 A4 CAS latency
A9
0
1
1
0
0
0
0
1
0
A9
0
0
1
1
X
A8
0
1
0
1
Data Sheet E0135H10
A8
0
1
0
1
X
Burst read and single write
Burst read and burst write
Write mode
R
R
A7
0
R
R
2
3
R
A6
LMODE
A5
A3
1
0 Sequential
Burst type
Interleave
A4
F.P. = Full Page
R is Reserved (inhibit)
X: 0 or 1
A3
BT
A2
A2 A1 A0
0
0
0
0
1
1
1
1
A1
BL
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A0
BT=0 BT=1
Burst length
F.P.
1
2
4
8
R
R
R
1
2
4
8
R
R
R
R