hm5264165f-75 Elpida Memory, Inc., hm5264165f-75 Datasheet - Page 31

• Manufacturer Part Number: hm5264165f-75
• Description: 64m Lvttl Interface Sdram
• Manufacturer: Elpida Memory, Inc.

Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the
same bank as the preceding write command, the read command can be performed after an interval of no less
than 1 clock. However, in the case of a burst write, data will continue to be written until one cycle before the
read command is executed.
WRITE to READ Command Interval (1)
WRITE to READ Command Interval (2)
DQMU/DQML
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write,
data will continue to be written until one clock before the read command is executed (as in the case of the
same bank and the same address).
DQMU/DQML
Command
Command
DQM,
DQM,
Dout
CLK
Dout
CLK
Din
Din
Column = A
Write
WRIT
in A0
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
Column = A
Write
WRIT
in A0
Data Sheet E0135H10
in A1
Column = B
Read
READ
Column = B
Read
READ
Column = B
Dout
out B0
Column = B
Dout
CAS Latency
out B0
CAS Latency
out B1
out B1
out B2
out B2
out B3
out B3
Burst Write Mode
CAS Latency = 2
Burst Length = 4
Bank 0
Burst Write Mode
CAS Latency = 2
Burst Length = 4
Bank 0
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