hm5264165f-75 Elpida Memory, Inc., hm5264165f-75 Datasheet - Page 57

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hm5264165f-75

Manufacturer Part Number
hm5264165f-75
Description
64m Lvttl Interface Sdram
Manufacturer
Elpida Memory, Inc.
Datasheet
Mode Register Set Cycle
Read Cycle/Write Cycle
DQMU/DQML
DQMU/DQML
DQMU/DQML
DQ (output)
DQ (output)
DQ (output)
DQ (input)
DQ (input)
DQ (input)
Address
Address
Address
DQM,
DQM,
CKE
RAS
CAS
CKE
RAS
CAS
DQM,
CLK
WE
WE
CS
CS
CKE
RAS
CAS
BS
BS
CLK
WE
CS
BS
V
V
IH
IH
Bank 0
Active
Bank 0
Active
R:a
R:a
V
Precharge
If needed
0
IH
valid
0
1
2
1
l RP
Bank 0
Read
Bank 0
Write
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
C:a
a
C:a
3
2
Mode
register
Set
a+1 a+2 a+3
4
code
Data Sheet E0135H10
Bank 3
Active
Bank 3
Active
3
l
R:b
R:b
RSA
5
Bank 3
Active
a
R: b
4
6
a+1 a+2 a+3
7
5
l RCD
Bank 3
Read
Bank 3
Write
b
C:b
C:b
8
6
Bank 0
Precharge
b+1 b+2 b+3 b'
9
Bank 3
Read
Bank 0
Precharge
C: b
7
High-Z
High-Z
10
High-Z
b
11
8
Bank 3
Read
Bank 3
Write
b+1 b+2 b+3 b'
C:b'
C:b'
12
9
Output mask
b'+1 b"
13
Bank 3
Read
Bank 3
Write
10
b
C:b"
C:b"
14
C: b’
b"+1 b"+2 b"+3
11
15
b'+1 b"
16
12
17
b+3
13
Bank 3
Precharge
Bank 3
Precharge
b"+1 b"+2 b"+3
18
14
b’
19
b’+1 b’+2
15
20
l
CAS latency = 3
Burst length = 4
Read cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
Write cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
RCD
16
= V
= V
= V
= 3
IH
IH
b’+3
IH
17
or V
or V
or V
IL
IL
18
IL
57

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