hm5264165f-75 Elpida Memory, Inc., hm5264165f-75 Datasheet - Page 24

• Manufacturer Part Number: hm5264165f-75
• Description: 64m Lvttl Interface Sdram
• Manufacturer: Elpida Memory, Inc.

HM5264165F/HM5264805F/HM5264405F-75/A60/B60
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write
operation, data is only written to the column address (AY0 to AY7; HM5264165F, AY0 to AY8;
HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (A12/A13) specified by the write
command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
Auto Precharge
Read with auto-precharge: In this operation, since precharge is automatically performed after completing a
read operation, a precharge command need not be executed after each read operation. The command executed
for the same bank after the execution of this command must be the bank active (ACTV) command. In
addition, an interval defined by l
CAS latency
3
2
Burst Read (Burst Length = 4)
24
CL=2 Command
CL=3 Command
DQ (input)
DQ (input)
CLK
Note: Internal auto-precharge starts at the timing indicated by "
Command
ACTV
ACTV
And an interval of t
Address
Din
CLK
RAS
(l
RAS
Precharge start cycle
2 cycle before the final data is output
1 cycle before the final data is output
) is required between previous active (ACTV) command and internal precharge "
APR
Data Sheet E0135H10
ACTV
Row
is required before execution of the next command.
l RAS
l RAS
t
RCD
READ A
READ A
".
Column
WRIT
in 0
out0
out1
out0
out1
out2
".
out3
out2
l APR
out3
ACTV
l APR
ACTV