hm5264165f-75 Elpida Memory, Inc., hm5264165f-75 Datasheet - Page 40

• Manufacturer Part Number: hm5264165f-75
• Description: 64m Lvttl Interface Sdram
• Manufacturer: Elpida Memory, Inc.

HM5264165F/HM5264805F/HM5264405F-75/A60/B60
DQM Control
The DQM mask the DQ data.
The DQMU and DQML mask the upper and lower bytes of the DQ data, respectively. The timing of
DQMU/DQML is different during reading and writing.
Reading: When data is read, the output buffer can be controlled by DQM, DQMU/DQML. By setting
DQM, DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output. By setting DQM,
DQMU/DQML to High, the output buffer becomes High-Z, and the corresponding data is not output.
However, internal reading operations continue. The latency of DQM, DQMU/DQML during reading is 2
clocks.
Writing: Input data can be masked by DQM, DQMU/DQML. By setting DQM, DQMU/DQML to Low,
data can be written. In addition, when DQM, DQMU/DQML is set to High, the corresponding data is not
written, and the previous data is held. The latency of DQM, DQMU/DQML during writing is 0 clock.
Reading
Writing
40
DQM,
DQMU/DQML
DQM,
DQMU/DQML
DQ (output)
DQ (input)
CLK
CLK
Data Sheet E0135H10
out 0
in 0
l
DOD
= 2 Latency
out 1
in 1
l
DID
High-Z
= 0 Latency
out 3
in 3