hm5264165f-75 Elpida Memory, Inc., hm5264165f-75 Datasheet - Page 52

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hm5264165f-75

Manufacturer Part Number
hm5264165f-75
Description
64m Lvttl Interface Sdram
Manufacturer
Elpida Memory, Inc.
Datasheet
HM5264165F/HM5264805F/HM5264405F-75/A60/B60
Notes: 1. AC measurement assumes t
Test Conditions
52
Input and output timing reference levels: 1.5 V
Input waveform and output load: See following figures
2. Access time is measured at 1.5 V. Load condition is CL = 50 pF.
3. t
4. t
5. t
6. t
t
LZ
HZ
CES
AS
DS
/t
/t
input
(min) defines the time at which the outputs achieves the low impedance state.
(max) defines the time at which the outputs achieves the high impedance state.
AH
DH
define CKE setup time to CLK rising edge except power down exit command.
: Address, t
: Data-in, t
2.4 V
0.4 V
CES
CS
2.0 V
0.8 V
/t
/t
CEH
CH
: CS, RAS, CAS, WE, DQM, DQMU/DQML
: CKE
Data Sheet E0135H10
t
T
T
= 1 ns. Reference level for timing of input signals is 1.5 V.
t
T
I/O
CL

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