hm5264165f-75 Elpida Memory, Inc., hm5264165f-75 Datasheet - Page 22

• Manufacturer Part Number: hm5264165f-75
• Description: 64m Lvttl Interface Sdram
• Manufacturer: Elpida Memory, Inc.

HM5264165F/HM5264805F/HM5264405F-75/A60/B60
Operation of the SDRAM
Read/Write Operations
Bank active: Before executing a read or write operation, the corresponding bank and the row address must be
activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to
the status of the A12/A13 pin, and the row address (AX0 to AX11) is activated by the A0 to A11 pins at the
bank active command cycle. An interval of t
following read/write command input.
Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in
the (CAS Latency - 1) cycle after read command set. HM5264165F, HM5264805F series, HM5264405F can
perform a burst read operation.
The burst length can be set to 1, 2, 4, 8 or full-page (256; HM5264165F, 512; HM5264805F, 1024;
HM5264405F). The start address for a burst read is specified by the column address (AY0 to AY7;
HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address
(A12/A13) at the read command set cycle. In a read operation, data output starts after the number of clocks
specified by the CAS Latency. The CAS Latency can be set to 2 or 3.
When the burst length is 1, 2, 4, 8, the Dout buffer automatically becomes High-Z at the next clock after the
successive burst-length data has been output.
The CAS latency and burst length must be specified at the mode register.
CAS Latency
Command
22
Address
Dout
CLK
CL = 2
CL = 3
ACTV
Row
t
RCD
Column
READ
Data Sheet E0135H10
RCD
is required between the bank active command input and the
out 0
out 0
out 1
out 2
out 1
out 3
out 2
out 3
CL = CAS latency
Burst Length = 4