ATAM893X-TKHYZ ATMEL [ATMEL Corporation], ATAM893X-TKHYZ Datasheet
ATAM893X-TKHYZ
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ATAM893X-TKHYZ Summary of contents
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Features • Extended Temperature Range for Very High Temperature up to 125°C • 4-Kbyte EEPROM Program Memory • EEPROM Programmable Options • Read Protection for the EEPROM Program Memory • 16 Bi-directional I/Os • Seven External/Internal Interrupt Sources ...
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Pin Configuration Figure 1-1. Pinning SSO20 Package Table 1-1. Pin Description Name Type Function VDD Supply voltage VSS Circuit ground BP10 I/O Bi-directional I/O line of Port 1.0 BP13 I/O Bi-directional I/O line of Port 1.3 BP20 I/O Bi-directional ...
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Introduction The ATAM893 member of Atmel’s family of 4-bit single-chip microcontrollers. Instead of ROM it contains EEPROM, RAM, parallel I/O ports, two 8-bit programmable multifunction timer/counters, voltage supervisor, interval timer with watchdog function and a sophisticated on- ...
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RC-oscillator Frequency The typical frequency of the internal RC-oscillator is about 5% higher for the Flash part com- pared to the ROM part. But due to the wide range of ±50% overall tolerances this should not affect the application ...
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Components of MARC4 Core The core contains ROM, RAM, ALU, program counter, RAM address registers, instruction decoder and interrupt controller. The following sections describe each functional block in more detail. 4.2.1 Program Memory The program memory (EEPROM) is programmable ...
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Return Stack The 12-bit wide return stack is addressed by the Return stack Pointer (RP used for storing return addresses of subroutines, interrupt routines and for keeping loop index counts. The return stack can also be used ...
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Figure 4-4. 4.2.3.2 RAM Address Registers The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These registers allow access to any of the 256 RAM nibbles. 4.2.3.3 Expression Stack Pointer (SP) The ...
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Top Of Stack (TOS) The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory refer- ence and I/O operations use this register. The TOS register receives data from the ALU, ROM, RAM or I/O bus. ...
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I/O Bus The I/O ports and the registers of the peripheral modules are I/O mapped. All communication between the core and the on-chip peripherals takes place via the I/O bus and the associated I/O control. With the MARC4 IN ...
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Interrupt Latency The interrupt latency is the time from the occurrence of the interrupt to the interrupt service rou- tine being activated. In MARC4 this is extremely short (taking between machine cycles depending on the state ...
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Table 4-2. Hardware Interrupts Interrupt Register INT1 P5CR INT2 INT3 INT4 T2CM T3CM1 INT5 T3CM2 INT6 P5CR INT7 4.2.7.3 Software Interrupts The programmer can generate interrupts by using the Software Interrupt Instruction (SWI) which is supported in qFORTH by predefined ...
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Figure 4-7. 4.3.1 Power-on Reset and Brown-out Detection The ATAM893-D has a fully integrated power-on reset and brown-out detection circuitry. For reset generation no external components are needed. These circuits ensure that the core is held in the reset state ...
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Figure 4-8. 4.3.2 Watchdog Reset The watchdog's function can be enabled at the WDC register and triggers a reset with every watchdog counter overflow. To suppress the watchdog reset, the watchdog counter must be regularly reset by reading the watchdog ...
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Figure 4-9. 4.4.1 Voltage Monitor Control/Status Register VMC: Write VMST: Read VM2: Voltage monitor Mode bit 2 VM1: Voltage monitor Mode bit 1 VM0: Voltage monitor Mode bit 0 Table 4-3. VM2 ...
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VIM VMS Figure 4-10. Internal Supply Voltage Supervisor Figure 4-11. External Input Voltage Supervisor 4.5 Clock Generation 4.5.1 Clock Module The ATAM893-D contains a clock module with 4 different internal oscillator types: two RC-oscil- lators, one 4-MHz crystal oscillator and ...
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The clock module is programmable via software with the clock management register (CM) and the system configuration register (SC). The required oscillator configuration can be selected with the OS1 bit and the OS0 bit in the SC register. A programmable ...
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Oscillator Circuits and External Clock Input Stage The ATAM893-D series consists of four different internal oscillators: two RC-oscillators, one 4- MHz crystal oscillator, one 32-kHz crystal oscillator and one external clock input stage. 4.5.2.1 RC-oscillator 1 Fully Integrated For ...
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Table 4-5. 4.5.2.3 RC-oscillator 2 with External Trimming Resistor The RC-oscillator high resolution trimmable oscillator whereby the oscillator frequency can be trimmed with an external resistor between OSC1 and V lator 2 frequency can be maintained stable ...
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Figure 4-17. Ceramic Resonator Note: 4.5.2.5 32-kHz Oscillator Some applications require long-term time keeping or low resolution timing. In this case, an on- chip, low power 32-kHz crystal oscillator can be used to generate both the SUBCL and the SYSCL. ...
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Clock Management Register (CM) CM: NSTOP CCS CSS1 CSS0 Table 4-6. 4.5.3.2 System Configuration Register (SC) SC: write BOT OS1 OS0 ATAM893-D 20 Bit 3 Bit 2 Bit 1 NSTOP CCS CSS1 Not STOP peripheral clock NSTOP = 0, ...
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Table 4-7. Mode Note: 4.6 Power-down Modes The sleep mode is a shut-down condition which is used to reduce the average system power consumption in applications where the microcontroller is not fully utilized. In this mode, ...
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Peripheral Modules 5.1 Addressing Peripherals Accessing the peripheral modules takes place via the I/O bus (see instructions allow direct addressing I/O modules. A dual register addressing scheme has been adopted to enable direct addressing of ...
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Table 5-1. Peripheral Addresses Port Address Name 1 P1DAT 2 P2DAT Auxiliary P2CR 3 SC CWD Auxiliary CM 4 P4DAT Auxiliary P4CR 5 P5DAT Auxiliary P5CR 6 P6DAT Auxiliary P6CR 7 T12SUB Subport address 0 T2C 1 T2M1 2 T2M2 ...
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Bi-directional Ports With the exception of Port 1 and Port 6, all other ports (2, 4 and 5) are 4 bits wide. Port 1 and Port 6 have a data width of 2 bits (bit 0 and bit 3). ...
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Figure 5-2. 5.2.2 Bi-directional Port 2 As all other bi-directional ports, this port includes a bit-wise programmable Control Register (P2CR), which enables the individual programming of each port bit as input or output. It also opens up the possibility of ...
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Figure 5-3. 5.2.2.1 Port 2 Data Register (P2DAT) P2DAT Bit 3 = MSB, Bit 0 = LSB 5.2.2.2 Port 2 Control Register (P2CR) P2CR Value 1111b means all pins in input mode Table 5-2. Code ...
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Bi-directional Port 5 As all other bi-directional ports, this port includes a bit-wise programmable Control Register (P5CR), which allows the individual programming of each port bit as input or output. It also opens up the possibility of reading the ...
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Figure 5-5. Port 5 External Interrupts Data in BP52 Bidir. Port IN_Enable I/O-bus Data in BP53 Bidir. Port IN_Enable P5CR: 5.2.3.1 Port 5 Data Register (P5DAT) P5DAT 5.2.3.2 Port 5 Control Register (P5CR) Byte Write P5CR P5xM2, P5xM1 – Port ...
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Table 5-3. Port 5 Control Register Auxiliary Address: '5'hex First Write Cycle Code Function BP50 in input mode – interrupt disabled BP50 in input mode – rising edge ...
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Port 4 Data Register (P4DAT) P4DAT 5.2.4.2 Port 4 Control Register (P4CR) Byte Write P4CR P4xM2, P4xM1 Table 5-4. Port 4 Control Register Auxiliary Address: '4'hex First Write Cycle Code Function ...
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Port 6 Data Register (P6DAT) P6DAT 5.2.5.2 Port 6 Control Register (P6CR) P6CR P6xM2, P6xM1 - Port 6x Interrupt mode/direction code Table 5-5. Code ...
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Figure 5-7. T3I T2I 5.3.1 Timer 1 The Timer interval timer which can be used to generate periodic interrupts and as pres- caler for Timer 2, Timer 3, the serial interface and the watchdog function. The Timer ...
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This timer starts running automatically after any power-on reset! If the watchdog function is not activated, the timer can be restarted by writing into the T1C1 register with T1RM = 1. Timer 1 can also be used as a watchdog ...
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Timer 1 Control Register 1 (T1C1) T1C1 Bit 3 = MSB, Bit 0 = LSB T1RM T1C2 T1C1 T1C0 The three bits T1C[2:0] select the divider for timer 1. The resulting time interval depends on this divider and the ...
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Timer 1 Control Register 2 (T1C2) T1C2 Bit 3 = MSB, Bit 0 = LSB T1BP T1CS T1IM 5.3.1.3 Watchdog Control Register (WDC) WDC Bit 3 = MSB, Bit 0 = LSB WDL WDR WDT1 WDT0 Both these bits ...
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Table 5-7. WDT1 5.3.2 Timer 2 Timer 8/12-bit timer used for: • Interrupt, square-wave, pulse and duty cycle generation • Baud-rate generation for the internal shift register • Manchester and Bi-phase modulation together ...
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The Timer 2 has a 4-bit compare register (T2CO1) and an 8-bit compare register (T2CO2). Both these compare registers are cascadable as a 12-bit compare register, or 8-bit compare register and 4-bit compare register. For 12-bit compare data value: For ...
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Mode 2: 8-bit Compare Counter with 4-bit Programmable Prescaler The 4-bit stage is used as a programmable prescaler for the 8-bit counter stage. In this mode, a duty cycle stage is also available. This stage can be used as an ...
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Timer 2 Output Modes The signal at the timer output is generated via modulator 2. In the toggle mode, the compare match event toggles the output T2O. For high resolution duty cycle modulation 8 bits or 12 bits can ...
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Toggle Mode B: A Timer 2 compare match toggles the output flip-flop (M2) Figure 5-16. Pulse Generator – the Timer Output Toggles with the Timer Start if the T2TS-bit Counter 2 Counter 2 Toggle Mode C: A Timer 2 compare ...
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Timer 2 Output Mode 2 Duty Cycle Burst Generator 1: The DCG output signal (DCGO) is given to the output, and gated by the output flip-flop (M2) Figure 5-18. Carrier Frequency Burst Modulation with Timer 2 Toggle Flip-flop Output Counter ...
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Timer 2 Output Mode 5 Manchester Modulator: Timer 2 Modulates the SSI internal data output (SO) to Manchester code Figure 5-21. Manchester Modulation Timer 2 Output Mode 7 PWM Mode: Pulse-width modulation output on Timer 2 output pin (T2O) In ...
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Timer 2 Control Register (T2C) T2C T2CS1 T2CS0 T2TS T2R Table 5-8. T2CS1 5.3.2.6 Timer 2 Mode Register 1 (T2M1) T2M1 T2D1 T2D0 T2MS1 T2MS0 Table 5-9. T2D1 4680C–4BMCU–01/05 Bit 3 Bit 2 Bit 1 ...
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Table 5-10. Mode 5.3.2.7 Duty Cycle Generator The duty cycle generator generates duty cycles of 25%, 33% or 50%. The frequency at the duty cycle generator output depends on the duty cycle and the Timer 2 ...
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Table 5-11. Output Mode If one of these output modes is used the T2O alternate function of Port 4 must also be activated. 5.3.2.9 Timer 2 Compare and Compare Mode Registers Timer 2 has two separate compare registers, T2CO1 for ...
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Timer 2 Compare Mode Register (T2CM) T2CM T2OTM T2CTM T2RM T2IM Table 5-12. Timer 2 Output Mode 5.3.2.11 Timer 2 COmpare Register 1 (T2CO1) T2CO1 In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0. ...
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Timer 3 5.3.3.1 Features • Two Compare Registers • Capture Register • Edge Sensitive Input with Zero Cross Detection Capability • Trigger and Single Action Modes • Output Control Modes • Automatic Modulation and Demodulation Modes • FSK Modulation ...
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A special feature of this timer is the trigger- and single-action mode. In trigger mode, the counter starts counting triggered by the external signal at its input. In single-action mode, the counter counts only one time up to the programmed ...
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Most of the timer modes use their compare registers alternately. After the start has been acti- vated, the first comparison is carried out via the compare register 1, the second is carried out via the compare register 2, the third ...
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Figure 5-27. Counter Reset with Compare Register 2 and Toggle with Start Figure 5-28. Single Action of Compare Register 1 Counter 3 Timer 3 – Mode 2: The counter is driven by an internal clock source. After starting with T3R, ...
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Timer 3 – Mode 3: The counter is driven by an internal or external (T3I) clock source. The output toggle signal of Timer 2 resets the counter. The counter value before the reset is saved in the capture register. If ...
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Timer 3 – Mode 8: The two compare registers are used for generating two different time intervals. The SSI internal data output (SO) selects which compare register is used for the output frequency generation. A '0' level at the SSI ...
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Timer 3 – Mode 10: Manchester Demodulation/Pulse-width Demodulation For Manchester demodulation, the edge detection stage must be programmed to detect each edge at the input. These edges are evaluated by the demodulator stage. The timer stage is used to generate ...
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Timer 3 – Mode 12: Timer/Counter with External Capture Mode (T3I) The counter is driven by an internal clock source and an edge at the external input T3I loads the counter value into the capture register. The edge can be ...
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Timer 3 Demodulator for Bi-phase, Manchester and Pulse-width-modulated Signals The demodulator stage of Timer 3 can be used to decode Bi-phase, Manchester and pulse- width-coded signals Figure 5-37. Timer 3 Demodulator 3 5.3.3.6 Timer 3 Registers 5.3.3.7 Timer 3 ...
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Table 5-13. Mode Note: 5.3.3.8 Timer 3 Control Register 1 (T3C) Write Write T3EIM T3TOP T3TS T3R ATAM893-D 56 Timer 3 Mode Select Bits (Continued) T3M3 T3M2 T3M1 T3M0 1 0 ...
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Timer 3 Status Register 1 (T3ST) Read Read T3ED T3C2 T3C1 Note: 5.3.3.10 Timer 3 Clock Select Register (T3CS) T3CS T3E1 T3E0 Table 5-14. T3E1 T3CS1 T3CS0 Table 5-15. T3CS1 4680C–4BMCU–01/05 Bit 3 Bit T3ED ...
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Timer 3 Compare- and Compare Mode Register Timer 3 has two separate compare registers T3CO1 and T3CO2 for the 8-bit stage of Timer 3. The timer compares the content of the compare register with the current counter value. If ...
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Timer 3 Compare Mode Register 2 (T3CM2) T3CM2 T3SM2 T3TM2 T3RM2 T3IM2 T3CM2 contains the mask bits for the match event of Counter 3 compare register 2 The compare registers and corresponding counter reset masks can be used to ...
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Timer 3 Capture Register The counter content can be read via the capture register. There are two ways to use the capture register. In modes 1 and possible to read the current counter value directly out ...
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SSI Peripheral Configuration The synchronous serial interface (SSI) can be used either for serial communication with external devices such as Proems, shift registers, display drivers, other microcontrollers means for generating and capturing on-chip serial streams of ...
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General SSI Operation The SSI is comprised essentially of an 8-bit shift register with two associated 8-bit buffers the receive buffer (SRB) for capturing the incoming serial data and a transmit buffer (STB) for inter- mediate storage of data ...
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Synchronous Mode Figure 5-39. 8-bit Synchronous Mode In the 8-bit synchronous mode, the SSI can operate as either 3-wire interface (see sec- tion “SSI Peripheral Configuration”). The serial data (SD) is received or transmitted in ...
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Figure 5-40. Example of an 8-bit Synchronous Transmit Operation Figure 5-41. Example of an 8-bit Synchronous Receive Operation SIR SRDY ACT Interrupt (IFN = 0) Interrupt (IFN = 1) ATAM893 msb lsb ...
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Shift Mode In the 9-bit shift mode, the SSI is able to handle the MCL protocol (described below). It always operates as an MCL master device, i.e always generated and output by the SSI. Both the ...
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Figure 5-43. Example of MCL Receive Dialog SRDY Interrupt (IFN = 0) Interrupt (IFN = 1) 5.3.4.6 8-bit Pseudo MCL Mode In this mode, the SSI exhibits all the typical MCL operational features except for the acknowl- edge-bit which is ...
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Figure 5-44. MCL Bus Protocol Bus not busy (1) Start data transfer (2) Stop data transfer (3) Data valid (4) Acknowledge Figure 5-45. MCL Bus Protocol 5.3.4.8 SSI Interrupt The SSI interrupt INT3 can ...
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Modulation and Demodulation If the shift register is used together with Timer 2 or Timer 3 for modulation or demodulation pur- poses, the 8-bit synchronous mode must be used. In this case, the unused Port 4 pins can be ...
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Serial Interface Registers 5.3.4.12 Serial Interface Control Register 1 (SIC1) SIC1 SIR SCD Note: SCS1 SCS0 Note: Table 5-16. • In transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded (SRDY = 1). ...
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Serial Interface Control Register 2 (SIC2) SIC2 MSM SM1 SM0 Table 5-17. Mode SDD Note: ATAM893-D 70 Bit 3 Bit 2 MSM SM1 Modular Stop Mode MSM = 1, modulator stop mode disabled (output masking off) MSM = 0, ...
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Serial Interface Status and Control Register (SISC) SISC write SISC read MCL RACK TACK SIM IFN SRDY ACT 4680C–4BMCU–01/05 Bit 3 Bit 2 Bit 1 MCL RACK SIM - - - TACK ACT Multi-Chip Link activation MCL = 1, ...
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Serial Transmit Buffer (STB) – Byte Write First write cycle Second write cycle T he STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift regi star ts shifting with 5.3.4.16 Serial ...
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Combination Mode Timer 2 and SSI Figure 5-48. Combination Timer 2 and SSI T2I SYSCL CL2/1 T1OUT TOG3 SCL RES T2C I/O-bus Combination Mode 1: Burst Modulation SSI mode 1: Timer 2 mode Timer ...
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Combination Mode 2: Bi-phase Modulation 1 SSI mode 1: Timer 2 mode Timer 2 output mode 4: Figure 5-50. Bi-phase Modulation 1 Combination Mode 3: Manchester Modulation 1 SSI mode 1: Timer 2 mode 1, ...
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Combination Mode 4: Manchester Modulation 2 SSI mode 1: Timer 2 mode 3: Timer 2 output mode 5: The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2. The SSI has ...
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Figure 5-53. Bi-phase Modulation 2 Counter 2/1 5.3.5.2 Combination Mode Timer 3 and SSI Figure 5-54. Combination Timer 3 and SSI T3CS T3I T3EX CL3 SYSCL T1OUT POUT RES Compare 3/1 T3CO1 TOG2 POUT T1OUT SYSCL ATAM893-D 76 SCLI Buffer ...
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Combination Mode 6: FSK Modulation SSI mode 1: Timer 3 mode 8: The two compare registers are used to generate two varied time intervals. The SSI data output selects which compare register is used for the output frequency generation. A ...
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Combination Mode 8: Manchester Demodulation/Pulse-width Demodulation SSI mode 1: Timer 3 mode 10: For Manchester demodulation, the edge detection stage must be programmed to detect each edge at the input. These edges are evaluated by the demodulator stage. The timer ...
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Combination Mode 9: Bi-phase Demodulation SSI mode 1: Timer 3 mode 11: In the Bi-phase demodulation mode the timer works like in the Manchester demodulation mode. The difference is that the bits are decoded with the toggle flip-flop. This flip-flop ...
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Combination Mode Timer 2 and Timer 3 Figure 5-59. Combination Timer 3 and Timer 2 T3CS T3I T3EX CL3 SYSCL T1OUT POUT RES Compare 3/1 T3CO1 T2I TOG3 CL2/1 SYSCL 4-bit Counter 2/1 T1OUT SCL RES T2C I/O-bus Combination ...
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Figure 5-60. Frequency Measurement Counter 3 Register Figure 5-61. Event Counter with Time Gate Counter 3 Register Combination Mode 11: Burst Modulation 1 Timer 2 mode 1/2: Timer 2 output mode 1/6: Timer 3 mode 6: The Timer 3 counter ...
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Combination Timer 2, Timer 3 and SSI Figure 5-63. Combination Timer 2, Timer 3 and SSI T3CS T3I T3EX CL3 SYSCL 8-bit Counter 3 T1OUT POUT RES Compare 3/1 T3CO1 T2I TOG3 CL2/1 SYSCL 4-bit Counter 2/1 T1OUT SCL ...
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Combination Mode 12: Burst Modulation 2 SSI mode 1: Timer 2 output mode 2: Timer 2 output mode 1/6: Timer 3 mode 7: The Timer 3 counter is driven by an internal or external clock source. Its compare- and compare ...
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Figure 5-65. FSK Modulation Counter 3 6. Data EEPROM The internal data EEPROM offers 2 pages of 512 bits each. Both pages are organized bit words. The programming voltage as well as the write cycle timing is ...
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Serial Interface The EEPROM uses an MCL-like two-wire serial interface to the microcontroller for read and write accesses to the data considered slave in all these applications. That means, the controller has to be ...
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Control Byte Format Start Start 6.2 EEPROM The EEPROM has a size of 2 and write data to and from the EEPROM the serial interface must be used. The interface sup- ports one and two byte write accesses and ...
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Write One Data Byte Start 6.2.2.3 Write Two Data Bytes Start 6.2.2.4 Write Control Byte Only Start 6.2.2.5 Write Control Bytes Write low byte first Byte order Write high byte first Byte order A acknowledge; HB: high byte; LB: ...
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Read One Data Byte Start 6.2.3.2 Read Two Data Bytes Start 6.2.3.3 Read n Data Bytes Start 6.2.3.4 Read Control Bytes Read low byte first, address increment Byte order Read high byte first, address decrement Byte order A acknowledge, ...
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Absolute Maximum Ratings Voltages are given relative to V SS. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these ...
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DC Operating Characteristics (Continued -40 to 125°C unless otherwise specified. SS amb Parameters Power-on Reset Threshold Voltage POR threshold voltage POR threshold voltage POR hysteresis Voltage Monitor Threshold Voltage VM high threshold voltage ...
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AC Characteristics Supply voltage V = 1 Parameters Operation Cycle Time System clock cycle Timer 2 input Timing Pin T2I Timer 2 input clock Timer 2 input LOW time Timer 2 input HIGH ...
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AC Characteristics (Continued) Supply voltage V = 1 Parameters 32-kHz Crystal Oscillator (Operating Range V Frequency Start-up time Stability Integrated input/output capacitances (configurable) External 32-kHz Crystal Parameters Crystal frequency Serial resistance Static capacitance ...
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Emulation The basic function of emulation is to test and evaluate the customer's program and hardware in real time. This therefore enables the analysis of any timing, hardware or software problem. For emulation purposes, all MARC4 controllers include a ...
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... Ordering Information (1) Extended Type Number ATAM893x-TKSYz ATAM893x-TKQYz ATAM893x-TKHYz Note Hardware revision z = Operating temperature range = D (-40°C to +125° Lead-free 14. Package Information Package SSO20 Dimensions in mm 0.25 0. ATAM893-D 94 Program Memory Data-EEPROM 4 kB Flash 2x512 Bit 4 kB Flash 2x512 Bit 4 kB Flash 2x512 Bit 6 ...
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Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4680C-4BMCU-01/05 4680B-4BMCU-05/04 4680C–4BMCU–01/05 History Put datasheet in a new template. Rename ATAM893-J in ...
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Table of Contents Features ..................................................................................................... 1 Description ................................................................................................ 1 1 Pin Configuration ..................................................................................... 2 2 Introduction .............................................................................................. 3 3 Differences Between ATAM893-D and ATARx90/x92 ........................... 3 4 MARC4 Architecture ................................................................................ 4 5 Peripheral Modules ................................................................................ 22 6 Data EEPROM ...
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Emulation ................................................................................................ 93 13 Ordering Information ............................................................................. 94 14 Package Information ............................................................................. 94 15 Revision History ..................................................................................... 95 4680C–4BMCU–01/05 ATAM893-D 97 ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...