ATAM893X-TKHYZ ATMEL [ATMEL Corporation], ATAM893X-TKHYZ Datasheet - Page 56
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ATAM893X-TKHYZ
Manufacturer Part Number
ATAM893X-TKHYZ
Description
Flash Version for ATAR080, ATAR090/890 and ATAR092/892
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATAM893X-TKHYZ.pdf
(98 pages)
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5.3.3.8
56
ATAM893-D
Timer 3 Control Register 1 (T3C) Write
Table 5-13.
Note:
T3EIM
T3TOP
T3TS
T3R
Mode
Write
10
11
12
13
14
15
16
8
9
1. In this mode, the SSI can be used only as demodulator (8-bit NRZ rising edge). All other SSI
T3M3
modes are not allowed.
1
0
0
0
0
0
0
0
0
Timer 3 Edge Interrupt Mask
T3EIM = 0, disables the interrupt when an edge event for Timer 3 occurs (T3I)
T3EIM = 1, enables the interrupt when an edge event for Timer 3 occurs (T3I)
Timer 3 Toggle Output Preset T3TOP = 0, sets toggle output (M3) to '0'
Timer 3 Toggle with Start . T3TS = 0, Timer 3 output is not toggled during the start
Timer 3 Run
Timer 3 Mode Select Bits (Continued)
T3M2
T3EIM
Bit 3
0
1
1
1
1
0
0
0
0
T3M1
............. ...... T3TOP = 1, sets toggle output (M3) to '1'
............. ...... Note: If T3R = 1, no output preset is possible
...... ...... T3TS = 1, Timer 3 output is toggled if started with T3R
...... ...... T3R = 0, Timer 3 stop and reset
...... ...... T3R = 1, Timer 3 run
0
1
1
0
0
1
1
0
0
T3TOP
Bit 2
T3M0
0
1
0
1
0
1
0
1
0
T3TS
Bit 1
Timer 3 Modes
FSK modulation with shift register (SO)
Pulse-width modulation with shift register (SO) and
Timer 2 (TOG2), internal trigger restart (SCO)
reset
Manchester demodulation/pulse-width demodulation
(T2O
Bi-phase demodulation
Timer/counter with external capture mode (T3I)
Not allowed
Not allowed
Not allowed
Not allowed
T3O)
Primary register address: 'C'hex — Write
Bit 0
T3R
(1)
(T2O
T3O)
Reset value: 0000b
4680C–4BMCU–01/05
counter
(1)
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