ATAM893X-TKHYZ ATMEL [ATMEL Corporation], ATAM893X-TKHYZ Datasheet - Page 20
ATAM893X-TKHYZ
Manufacturer Part Number
ATAM893X-TKHYZ
Description
Flash Version for ATAR080, ATAR090/890 and ATAR092/892
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATAM893X-TKHYZ.pdf
(98 pages)
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4.5.3.1
4.5.3.2
20
ATAM893-D
Clock Management Register (CM)
System Configuration Register (SC)
Table 4-6.
CM:
NSTOP
CCS
CSS1
CSS0
SC: write
BOT
OS1
OS0
CSS1
0
1
1
0
Not STOP peripheral clock
NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode
NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode
Core Clock Select
CCS = 1, the internal RC-oscillator 1 generates SYSCL
CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external
Core Speed Select 1
Core Speed Select 0
Bit 3
NSTOP
Core Speed Select
Bit 3
BOT
Brown-Out Threshold
BOT = 1, low brown-out voltage threshold (1.65 V)
BOT = 0, high brown-out voltage threshold (1.95 V)
Oscillator Select 1
Oscillator Select 0
clock source or the RC-oscillator 2 with the external resistor at OSC1
generates SYSCL dependent on the setting of OS0 and OS1 in the
system configuration register
Bit 2
CCS
Bit 2
–
CSS0
0
1
0
1
Bit 1
CSS1
Bit 1
OS1
Bit 0
CSS0
Bit 0
OS0
Divider
Primary register address: '3'hex
Auxiliary register address:
Reset value: 1111b
Reset value: 1x11b
16
8
4
2
Reset value
4680C–4BMCU–01/05
Note
'3'hex
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