ATAM893X-TKHYZ ATMEL [ATMEL Corporation], ATAM893X-TKHYZ Datasheet - Page 32

• Manufacturer Part Number: ATAM893X-TKHYZ
• Description: Flash Version for ATAR080, ATAR090/890 and ATAR092/892
• Manufacturer: ATMEL [ATMEL Corporation]

5.3.1
32
ATAM893-D
Timer 1
Figure 5-7.
The Timer 1 is an interval timer which can be used to generate periodic interrupts and as pres-
caler for Timer 2, Timer 3, the serial interface and the watchdog function.
The Timer 1 consists of a programmable 14-stage divider that is driven by either SUBCL or
SYSCL. The timer output signal can be used as prescaler clock or as SUBCL and as source for
the Timer 1 interrupt. Because of other system requirements the Timer 1 output T1OUT is syn-
chronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU core
OSC-Stop
active in SLEEP and generate Timer 1 interrupts. The interrupt is maskable via the T1IM bit and
the SUBCL can be bypassed via the T1BP bit of the T1C2 register. The time interval for the
timer output can be programmed via the Timer 1 control register T1C1.
T3I
T2I
yes) the output T1OUT is stopped (T1OUT = 0). Nevertheless, the Timer 1 can be
SYSCL
UTCM Block Diagram
SUBCL
T1OUT
TOG3
POUT
TOG2
from clock module
MUX
MUX
MUX
MUX
MUX
DCG
Receive-Buffer
8-bit Shift-Register
Transmit-Buffer
Capture 3
8-bit Counter 3
Compare 3/1
Compare 3/2
4-bit Counter 2/1
Compare 2/1
8-bit Counter 2/2
Compare 2/2
Timer 1
Timer 3
Timer 2
Interval/Prescaler
Control
SSI
Watchdog
Control
Demodu-
Control
Modu-
Modu-
lator 3
lator 3
lator 2
SCL
I/O bus
NRST
INT2
INT5
INT4
INT3
4680C–4BMCU–01/05
T3O
T2O
SC
SD
sleep and