ATAM893X-TKHYZ ATMEL [ATMEL Corporation], ATAM893X-TKHYZ Datasheet - Page 4
ATAM893X-TKHYZ
Manufacturer Part Number
ATAM893X-TKHYZ
Description
Flash Version for ATAR080, ATAR090/890 and ATAR092/892
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATAM893X-TKHYZ.pdf
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3.5
3.6
4. MARC4 Architecture
4.1
4
RC-oscillator Frequency
High Drive Outputs
General Description
ATAM893-D
The typical frequency of the internal RC-oscillator is about 5% higher for the Flash part com-
pared to the ROM part. But due to the wide range of ±50% overall tolerances this should not
affect the application too much.
This 5% is also valid for the RC-oscillator with an external resistor. For a frequency of 4 MHz the
flash part requires a resistor of 180 k, while the ROM part only needs 170 k.
On request the ROM parts offer a high current output selection. These pins than are twice as
strong as in the standard configuration. The ATAM893-D does not offer this selection. Only the
Timer 2 output (BP42) and the Timer 3 output (BP60) are configured as high current outputs for
the low side driver by default. This configuration is fixed and cannot be changed by the
customer.
The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and on-chip
peripherals. The CPU is based on the Harvard architecture with physically separate program
memory (ROM) and data memory (RAM). Three independent buses, the instruction bus, the
memory bus and the I/O bus, are used for parallel communication between ROM, RAM and
peripherals. This enhances program execution speed by allowing both instruction prefetching,
and a simultaneous communication to the on-chip peripheral circuitry. The extremely powerful
integrated interrupt controller with associated eight prioritized interrupt levels supports fast and
efficient processing of hardware events. The MARC4 is designed for the high-level programming
language qFORTH. The core includes both, an expression and a return stack. This architecture
enables high-level language programming without any loss of efficiency or code density.
Figure 4-1.
MARC4 Core
System
Reset
clock
Clock
Sleep
Reset
Program
memory
Instruction
Interrupt
controller
decoder
Instruction
bus
I/O bus
On-chip peripheral modules
MARC4 CORE
PC
Memory bus
CCR
SP
RP
X
Y
TOS
ALU
256 x 4-bit
RAM
4680C–4BMCU–01/05
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