ATAM893X-TKHYZ ATMEL [ATMEL Corporation], ATAM893X-TKHYZ Datasheet - Page 22

• Manufacturer Part Number: ATAM893X-TKHYZ
• Description: Flash Version for ATAR080, ATAR090/890 and ATAR092/892
• Manufacturer: ATMEL [ATMEL Corporation]

5. Peripheral Modules
5.1
22
Addressing Peripherals
ATAM893-D
Accessing the peripheral modules takes place via the I/O bus (see
instructions allow direct addressing of up to 16 I/O modules. A dual register addressing scheme
has been adopted to enable direct addressing of the primary register. To address the auxiliary
register, the access must be switched with an auxiliary switching module. Thus, a single IN (or
OUT) to the module address will read (or write into) the module primary register. Accessing the
auxiliary register is performed with the same instruction preceded by writing the module address
into the auxiliary switching module. Byte wide registers are accessed by multiple IN- (or OUT-)
instructions. For more complex peripheral modules, with a larger number of registers, extended
addressing is used. In this case a bank of up to 16 subport registers are indirectly addressed
with the subport address. The first OUT-instruction writes the subport address to the subaddress
register, the second IN- or OUT-instruction reads data from or writes data to the addressed
subport.
Figure 5-1.
Aux._Data = Data to be written into Auxiliary Register
Aux._Data (lo) = Data to be written into Auxiliary Register (low nibble)
Addr. (Mx) = Module Mx Address
Addr. (SPort) = Subport Address
Prim._Data = Data to be written into Primary Register
Addr. (ASW) = Auxililiary Switch Module Address
Example of
qFORTH
Program
Code
Module ASW
Auxiliary Switch
Primary Reg.
Module
Example of I/O Addressing
2
1
2
2
2
1
2
2
1
1
(Address Pointer)
Subaddress Reg.
SPort_Data
(Subport Register Read)
Addr. (SPort) Addr. (M1) OUT
(Subport Register Write Byte)
Addr. (SPort) Addr. (M1) OUT
SPort_Data (lo) Addr. (M1)
SPort_Data (hi) Addr. (M1)
(Subport Register Read Byte)
Addr. (SPort) Addr. (M1) OUT
Addr. (SPort) Addr. (M1) OUT
(Subport Register Write)
1
Indirect Subport Access
Module M1
Addr. (M1)
Addr. (M1) IN (hi)
Addr. (M1) IN (lo)
Addr. (M1) IN
Bank of
Primary Regs.
Subport EH
Subport FH
Subport 0
Subport 1
OUT
OUT
OUT
2
Aux._Data (hi) = Data to be written into Auxiliary Register (high nibble)
SPort_Data (lo) = Data to be written into Subport (low nibble)
SPort_Data (hi) = Data to be written into Subport (high nibble)
(lo) = SPort_Data (low nibble)
(hi) = SPort_Data (high nibble)
I/O bus
3
4
5
3
4
5
4
5
5
Addr. (M2) Addr. (ASW) OUT
Addr. (M2) Addr. (ASW) OUT
Aux._Data Addr. (M2) OUT
Prim._Data Addr. (M2) OUT
Aux._Data (lo) Addr. (M2)
Aux._Data (hi) Addr. (M2)
(Auxiliary Register Read )
(Primary Register Write)
(Primary Register Read)
Addr. (M2) Addr. (ASW) OUT
Aux. Reg.
(Auxiliary Register Write)
(Auxiliary Register Write Byte)
5
Dual Register Access
4
Module M2
Addr. (M2) IN
Addr. (M2) IN
Primary Reg.
3
OUT
OUT
6
6
to other modules
Figure
Single Register Access
Prim._Data Addr. (M3) OUT
(Primary Register Write)
(Primary Register Read)
Module M3
Primary Reg.
Addr. (M3) IN
5-1). The IN or OUT
6
4680C–4BMCU–01/05