ATAM893X-TKHYZ ATMEL [ATMEL Corporation], ATAM893X-TKHYZ Datasheet - Page 53

• Manufacturer Part Number: ATAM893X-TKHYZ
• Description: Flash Version for ATAR080, ATAR090/890 and ATAR092/892
• Manufacturer: ATMEL [ATMEL Corporation]

4680C–4BMCU–01/05
Timer 3 – Mode 10: Manchester Demodulation/Pulse-width Demodulation
For Manchester demodulation, the edge detection stage must be programmed to detect each
edge at the input. These edges are evaluated by the demodulator stage. The timer stage is used
to generate the shift clock for the SSI. The compare register 1 match event defines the correct
moment for shifting the state from the input T3I as the decoded bit into shift register - after that
the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. The
compare register 2 can also be used to detect a time-out error and handle it with an interrupt
routine (see section “Combination Mode 8”).
Figure 5-33. Manchester Demodulation
Timer 3 – Mode 11: Bi-phase Demodulation
In the Bi-phase demodulation mode, the timer operates like in Manchester demodulation mode.
The difference is that the bits are decoded via a toggle flip-flop. This flip-flop samples the edge in
the middle of the bit-frame and the compare register 1 match event shifts the toggle flip-flop out-
put into a shift register (see section “Combination Mode 9”).
Figure 5-34. Bi-phase Demodulation
CM31 = SCI
CM31 = SCI
SR-DATA
Counter 3
Q1 = SI
Timer 3
SR DATA
mode
T3EX
Timer 3
Reset
mode
T3EX
T3I
T3I
SI
Synchronize
Synchronize
1
0
0
0
BIT 0
BIT 0
1
0
1
1
BIT 1
BIT 1
1
1
1
1
Manchester demodulation mode
Biphase demodulation mode
BIT 2
BIT 2
1
1
1
0
BIT 3
0
BIT 3
0
1
0
BIT 4
0
BIT 4
1
0
0
BIT 5
ATAM893-D
BIT 5
0
1
1
1
BIT 6
BIT 6
1
1
1
0
0
0
0
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