ATAM893X-TKHYZ ATMEL [ATMEL Corporation], ATAM893X-TKHYZ Datasheet - Page 8

• Manufacturer Part Number: ATAM893X-TKHYZ
• Description: Flash Version for ATAR080, ATAR090/890 and ATAR092/892
• Manufacturer: ATMEL [ATMEL Corporation]

4.2.3.6
4.2.3.7
4.2.3.8
4.2.3.9
4.2.3.10
4.2.4
8
ATAM893-D
ALU
Top Of Stack (TOS)
Condition Code Register (CCR)
Carry/Borrow (C)
Branch (B)
Interrupt Enable (I)
The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory refer-
ence and I/O operations use this register. The TOS register receives data from the ALU, ROM,
RAM or I/O bus.
The 4-bit wide condition code register contains the branch, the carry and the interrupt enable
flag. These bits indicate the current state of the CPU. The CCR flags are set or reset by ALU
operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow direct manipulation of the
condition code register.
The carry/borrow flag indicates that the borrowing or carrying out of Arithmetic Logic Unit (ALU)
occurred during the last arithmetic operation. During shift and rotate operations, this bit is used
as a fifth bit. Boolean operations have no affect on the C-flag.
The branch flag controls the conditional program branching. Should the branch flag have been
set by a previous instruction, a conditional branch will cause a jump. This flag is affected by
arithmetic, logic, shift, and rotate operations.
The interrupt enable flag globally enables or disables the triggering of all interrupt routines with
the exception of the non-maskable reset. After a reset or on executing the DI instruction, the
interrupt enable flag is reset, thus disabling all interrupts. The core will not accept any further
interrupt requests until the interrupt enable flag has been set again by either executing an EI,
RTI or SLEEP instruction.
The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two ele-
ments of the expression stack (TOS and TOS-1) and returns the result to the TOS. The ALU
operations affect the carry/borrow and branch flag in the condition code register (CCR).
Figure 4-5.
ALU Zero-address Operations
SP
RAM
TOS-1
TOS-2
TOS-3
TOS-4
CCR
ALU
TOS
4680C–4BMCU–01/05