SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 16

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
8.2.1.4 Status register
Table 7.
The Status register is a 2 B read-only register used to record status information on PCI
bus-related events. For bit allocation, see
Table 8.
Table 9.
Bit
2
1
0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
15
14
13
12
11
Symbol
DPE
SSE
RMA
RTA
STA
Command register (address 04h) bit description
Status register (address 06h) bit allocation
Status register (address 06h) bit description
Symbol
BM
MS
IOS
FBBC
DPE
15
R
R
0
7
0
reserved
Description
Detected Parity Error: This bit must be set by the device whenever it
detects a parity error, even if the parity error handling is disabled.
Signaled System Error: This bit must be set whenever the device asserts
SERR#. Devices that never assert SERR# do not need to implement this
bit.
Received Master Abort: This bit must be set by a master device whenever
its transaction, except for Special Cycle, is terminated with Master-Abort.
All master devices must implement this bit.
Received Target Abort: This bit must be set by a master device whenever
its transaction is terminated with Target-Abort. All master devices must
implement this bit.
Signaled Target Abort: This bit must be set by a target device whenever it
terminates a transaction with Target-Abort. Devices that never signal
Target-Abort do not need to implement this bit.
Rev. 01 — 7 February 2007
SSE
Description
Bus Master: Controls the ability of a device to act as a master on the PCI
bus.
0 — Disables the device from generating PCI accesses. State after
RST# is logic 0.
1 — Allows the device to behave as a bus master.
Memory Space: Controls the response of a device to Memory Space
accesses.
0 — Disables the device response. State after RST# is logic 0.
1 — Allows the device to respond to memory space accesses.
IO Space: Controls the response of a device to I/O space accesses.
0 — Disables the device response. State after RST# is logic 0.
1 — Allows the device to respond to I/O space accesses.
14
R
R
0
6
0
66MC
RMA
13
R
R
0
5
0
Hi-Speed Universal Serial Bus PCI Host Controller
Table
RTA
CL
12
R
R
0
4
1
8.
STA
11
R
R
0
3
0
…continued
DEVSELT[1:0]
10
R
R
2
0
0
reserved
SAF1562
© NXP B.V. 2007. All rights reserved.
R
R
9
1
1
0
MDPE
16 of 97
R
R
8
0
0
0