SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 69

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
Table 96.
Address: Value read from func2 of address 10h + 28h
[1]
Table 97.
Address: Value read from func2 of address 10h + 28h
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 6
5
4
3
2
1
0
The reserved bits should always be written with the reset value.
USBINTR - USB Interrupt Enable register bit allocation
USBINTR - USB Interrupt Enable register bit description
Symbol
reserved
IAAE
HSEE
FLRE
PCIE
USB
ERRINTE
USBINTE
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
reserved
R/W
R/W
R/W
R/W
Rev. 01 — 7 February 2007
[1]
30
22
14
Description
-
Interrupt on Asynchronous Advance Enable: When this bit and IAA
(bit 5 in the USBSTS register) are set, the Host Controller issues an
interrupt at the next interrupt threshold. The interrupt is acknowledged by
software clearing bit IAA.
Host System Error Enable: When this bit and HSE (bit 4 in the USBSTS
register) are set, the Host Controller issues an interrupt. The interrupt is
acknowledged by software clearing bit HSE.
Frame List Rollover Enable: When this bit and FLR (bit 3 in the
USBSTS register) are set, the Host Controller issues an interrupt. The
interrupt is acknowledged by software clearing bit FLR.
Port Change Interrupt Enable: When this bit and PCD (bit 2 in the
USBSTS register) are set, the Host Controller issues an interrupt. The
interrupt is acknowledged by software clearing bit PCD.
USB Error Interrupt Enable: When this bit and USBERRINT (bit 1 in the
USBSTS register) are set, the Host Controller issues an interrupt at the
next interrupt threshold. The interrupt is acknowledged by software
clearing bit USBERRINT.
USB Interrupt Enable: When this bit and USBINT (bit 0 in the USBSTS
register) are set, the Host Controller issues an interrupt at the next
interrupt threshold. The interrupt is acknowledged by software clearing
bit USBINT.
0
0
0
6
0
IAAE
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Hi-Speed Universal Serial Bus PCI Host Controller
HSEE
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
reserved
FLRE
R/W
R/W
R/W
R/W
27
19
11
[1]
[1]
[1]
0
0
0
3
0
PCIE
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
ERRINTE
SAF1562
© NXP B.V. 2007. All rights reserved.
USB
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
USBINTE
R/W
R/W
R/W
R/W
69 of 97
24
16
0
0
8
0
0
0