SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 64

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
11.2.4 HCSP-PORTROUTE register
11.3.1 USBCMD register
11.3 Operational registers of Enhanced USB Host Controller
The HCSP-PORTROUTE (Companion Port Route Description) register is an optional
read-only field that is valid only if PRR (bit 7 in the HCSPARAMS register) is logic 1. Its
address is value read from func2 of address 10h + 0Ch.
This field is a 15-element nibble array—each 4 bits is one array element. Each array
location corresponds one-to-one with a physical port provided by the Host Controller. For
example, PORTROUTE[0] corresponds to the first PORTSC port, PORTROUTE[1] to the
second PORTSC port, and so on. The value of each element indicates to which of the
companion Host Controllers this port is routed. Only the first N_PORTS elements have
valid information. A value of zero indicates that the port is routed to the lowest numbered
function companion Host Controller. A value of one indicates that the port is routed to the
next lowest numbered function companion Host Controller, and so on.
The USB Command (USBCMD) register indicates the command to be executed by the
serial Host Controller. Writing to this register causes a command to be executed.
shows the bit allocation.
Table 92.
Address: Value read from func2 of address 10h + 20h
[1]
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
USBCMD - USB Command register bit allocation
LHCR
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Rev. 01 — 7 February 2007
IAAD
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
R/W
R/W
R/W
ASE
R/W
29
21
13
0
0
0
5
0
Hi-Speed Universal Serial Bus PCI Host Controller
PSE
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
ITC[7:0]
R/W
R/W
R/W
R/W
[1]
[1]
27
19
11
0
1
0
3
0
FLS[1:0]
R/W
R/W
R/W
R/W
26
18
10
2
0
0
0
0
SAF1562
© NXP B.V. 2007. All rights reserved.
RESET
R/W
R/W
R/W
R/W
HC
25
17
0
0
9
0
1
0
Table 92
R/W
R/W
R/W
R/W
64 of 97
RS
24
16
0
0
8
0
0
0