SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 77

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
Table 107. PORTSC 1, 2 - Port Status and Control 1, 2 register bit description
Address: Value read from func2 of address 10h + 64h + (4
is 1, 2
Bit
6
5
4
3
2
1
0
Symbol
FPR
OCC
OCA
PEDC
PED
ECSC
ECCS
Description
Force Port Resume: Logic 1 means resume detected or driven on the
port. Logic 0 means no resume (K-state) detected or driven on the port.
Default = logic 0. Software sets this bit to drive the resume signaling. The
Host Controller sets this bit if a J-to-K transition is detected, while the port
is in the suspend state. When this bit changes to logic 1 because a J-to-K
transition is detected, PCD (bit 2) in the USBSTS register is also set to
logic 1. If software sets this bit to logic 1, the Host Controller must not set
the PCD bit. When the EHCI controller owns the port, the resume
sequence follows the sequence specified in Universal Serial Bus
Specification Rev. 2.0 . The resume signaling (full-speed ‘K’) is driven on
the port as long as this bit remains set. Software must time the resume and
clear this bit after the correct amount of time has elapsed. Clearing this bit
causes the port to return to high-speed mode, forcing the bus below the
port into a high-speed idle. This bit will remain at logic 1, until the port has
switched to the high-speed idle. The Host Controller must complete this
transition within 2 ms of software clearing this bit.
Overcurrent Change: Default = logic 0. This bit is set to logic 1 when
there is a change in overcurrent active. Software clears this bit by setting it
to logic 1.
Overcurrent Active: Default = logic 0. If set to logic 1, this port has an
overcurrent condition. If set to logic 0, this port does not have an
overcurrent condition. This bit will automatically change from logic 1 to
logic 0 when the overcurrent condition is removed.
Port Enable/Disable Change: Logic 1 means the port enabled or disabled
status has changed. Logic 0 means no change. Default = logic 0. For the
root hub, this bit is set only when a port is disabled because of the
appropriate conditions existing at the EOF2 point. For definition of port
error, refer to Chapter 11 of Universal Serial Bus Specification Rev. 2.0 .
Software clears this bit by setting it.
Port Enabled/Disabled: Logic 1 means enable. Logic 0 means disable.
Default = logic 0. Ports can only be enabled by the Host Controller as a
part of the reset and enable sequence. Software cannot enable a port by
writing logic 1 to this field. The Host Controller will only set this bit when the
reset sequence determines that the attached device is a high-speed
device. Ports can be disabled by either a fault condition or by host
software. The bit status does not change until the port state has changed.
There may be a delay in disabling or enabling a port because of other Host
Controller and bus events. When the port is disabled, downstream
propagation of data is blocked on this port, except for reset.
Connect Status Change: Logic 1 means change in ECCS. Logic 0 means
no change. Default = logic 0. This bit indicates a change has occurred in
the ECCS of the port. The Host Controller sets this bit for all changes to the
port device connect status, even if the system software has not cleared an
existing connect status change. For example, the insertion status changes
two times before the system software has cleared the changed condition,
hub hardware will be setting an already-set bit, that is, the bit will remain
set. Software clears this bit by writing logic 1 to it.
Current Connect Status: Logic 1 indicates a device is present on the port.
Logic 0 indicates no device is present. Default = logic 0. This value reflects
the current state of the port and may not directly correspond to the event
that caused the ECSC bit to be set.
Rev. 01 — 7 February 2007
Hi-Speed Universal Serial Bus PCI Host Controller
[1]
[1]
Port Number
[1]
[1]
1) where Port Number
SAF1562
© NXP B.V. 2007. All rights reserved.
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