SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 47

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
11.1.12 HcBulkCurrentED register
11.1.13 HcDoneHead register
This register contains the physical address of the current endpoint of the bulk list. The
endpoints are ordered according to their insertion to the list because the bulk list must be
served in a round-robin fashion. The bit allocation is given in
Table 64.
Address: Value read from func0 or func1 of address 10h + 2Ch
[1]
Table 65.
Address: Value read from func0 or func1 of address 10h + 2Ch
The HcDoneHead register contains the physical address of the last completed TD that
was added to the Done queue. In normal operation, the HCD need not read this register
because its content is periodically written to the HCCA.
of the register.
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 4 BCED[27:0]
3 to 0
The reserved bits should always be written with the reset value.
Symbol
reserved
HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit
allocation
HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit
description
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
Description
Bulk Current ED: This is advanced to the next ED after the Host
Controller has served the current ED. The Host Controller continues
processing the list from where it left off in the last frame. When it reaches
the end of the bulk list, the Host Controller checks CLF (bit 1 of
HcCommandStatus). If the CLF bit is not set, nothing is done. If the CLF
bit is set, it copies the content of HcBulkHeadED to HcBulkCurrentED and
clears the CLF bit. The HCD can modify this register only when BLE (bit 5
in the HcControl register) is cleared. When HcControl is set, the HCD
reads the instantaneous value of this register. This is initially set to logic 0
to indicate the end of the bulk list.
-
Rev. 01 — 7 February 2007
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
BCED[3:0]
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Hi-Speed Universal Serial Bus PCI Host Controller
R/W
R/W
R/W
R/W
28
20
12
BCED[27:20]
BCED[19:12]
0
0
0
4
0
BCED[11:4]
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
Table 66
Table
R/W
R/W
R/W
R/W
26
18
10
2
contains the bit allocation
0
0
0
0
reserved
64.
SAF1562
© NXP B.V. 2007. All rights reserved.
R/W
R/W
R/W
R/W
[1]
25
17
0
0
9
0
1
0
R/W
R/W
R/W
R/W
47 of 97
24
16
0
0
8
0
0
0