SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 43

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
11.1.7 HcHCCA register
11.1.8 HcPeriodCurrentED register
The HcHCCA register contains the physical address of the Host Controller
Communication Area (HCCA). The bit allocation is given in
determines the alignment restrictions by writing all ones to HcHCCA and reading the
content of HcHCCA. The alignment is evaluated by examining the number of zeroes in the
lower order bits. The minimum alignment is 256 B; therefore, bits 0 through 7 will always
return logic 0 when read. This area is used to hold the control structures and the interrupt
table that are accessed by both the Host Controller and the HCD.
Table 54.
Address: Value read from func0 or func1 of address 10h + 18h
[1]
Table 55.
Address: Value read from func0 or func1 of address 10h + 18h
The HcPeriodCurrentED register contains the physical address of the current isochronous
or interrupt ED.
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 8
7 to 0
The reserved bits should always be written with the reset value.
HcHCCA - Host Controller Communication Area register bit allocation
HcHCCA - Host Controller Communication Area register bit description
R/W
R/W
R/W
R/W
Symbol
HCCA[23:0]
reserved
31
23
15
0
0
0
7
0
Table 56
Rev. 01 — 7 February 2007
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
shows the bit allocation of the register.
Description
Host Controller Communication Area Base Address: This is the
base address of the HCCA.
-
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Hi-Speed Universal Serial Bus PCI Host Controller
R/W
R/W
R/W
R/W
28
20
12
HCCA[23:16]
0
HCCA[15:8]
0
0
4
0
HCCA[7:0]
reserved
R/W
R/W
R/W
R/W
[1]
27
19
11
0
0
0
3
0
Table
R/W
R/W
R/W
R/W
26
18
10
2
0
0
0
0
54. The HCD
SAF1562
© NXP B.V. 2007. All rights reserved.
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
R/W
R/W
R/W
R/W
43 of 97
24
16
0
0
8
0
0
0