SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 54

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
11.1.20 HcRhDescriptorB register
Table 79.
Address: Value read from func0 or func1 of address 10h + 48h
The HcRhDescriptorB register is the second of two registers describing the characteristics
of the Root Hub. The bit allocation is given in
initialization to correspond to the system implementation. Reset values are
implementation-specific.
Table 80.
Address: Value read from func0 or func1 of address 10h + 4Ch
Bit
10
9
8
7 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Symbol
DT
NPS
PSM
NDP[7:0]
HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit description
…continued
HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit allocation
R/W
R/W
R/W
31
23
15
0
0
0
Description
Device Type: This bit specifies that the Root Hub is not a compound
device. The Root Hub is not permitted to be a compound device. This field
should always read logic 0.
No Power Switching: This bit is used to specify whether power switching is
supported or ports are always powered. It is implementation-specific. When
this bit is cleared, the PSM bit specifies global or per-port switching.
0 — Ports are power switched
1 — Ports are always powered on when the Host Controller is powered on
Power Switching Mode: This bit is used to specify how the power
switching of Root Hub ports is controlled. It is implementation-specific. This
field is only valid if the NPS field is cleared.
0 — All ports are powered at the same time
1 — Each port is individually powered. This mode allows port power to be
controlled by either the global switch or per-port switching. If the PPCM
(Port Power Control Mask) bit is set, the port responds only to port power
commands (Set/Clear Port Power). If the port mask is cleared, then the port
is controlled only by the global power switch (Set/Clear Global Power).
Number Downstream Ports: These bits specify the number of
downstream ports supported by the Root Hub. It is implementation-specific.
The minimum number of ports is 1. The maximum number of ports
supported by OHCI is 15.
Rev. 01 — 7 February 2007
R/W
R/W
R/W
30
22
14
0
0
0
R/W
R/W
R/W
29
21
13
0
0
0
Hi-Speed Universal Serial Bus PCI Host Controller
R/W
R/W
R/W
28
20
12
PPCM[15:0]
0
0
0
PPCM[7:0]
Table
DR[15:8]
80. These fields are written during
R/W
R/W
27
19
11
R
0
0
0
R/W
R/W
R/W
26
18
10
0
0
0
SAF1562
© NXP B.V. 2007. All rights reserved.
R/W
R/W
R/W
25
17
0
1
9
0
R/W
R/W
R/W
54 of 97
24
16
0
0
8
0