SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 75

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
Table 107. PORTSC 1, 2 - Port Status and Control 1, 2 register bit description
Address: Value read from func2 of address 10h + 64h + (4
is 1, 2
Bit
19 to 16
15 and 14 reserved
13
12
11 and 10 LS[1:0]
9
Symbol
PTC[3:0]
PO
PP
reserved
Description
Port Test Control: Default = 0000b. When this field is logic 0, the port is
not operating in test mode. A nonzero value indicates that it is operating in
test mode and test mode is indicated by the value. The encoding of the test
mode bits are:
0000b — Test mode disabled
0001b — Test J_STATE
0010b — Test K_STATE
0011b — Test SE0_NAK
0100b — Test packet
0101b — Test FORCE_ENABLE
0110b to 1111b — reserved
-
Port Owner: Default = logic 1. This bit unconditionally goes to logic 0
when CF (bit 0) in the CONFIGFLAG register makes logic 0 to logic 1
transition. This bit unconditionally goes to logic 1 when the CF bit is logic 0.
The system software uses this field to release ownership of the port to a
selected Host Controller, if the attached device is not a high-speed device.
Software writes logic 1 to this bit, if the attached device is not a high-speed
device. Logic 1 in this bit means that a companion Host Controller owns
and controls the port.
Port Power: The function of this bit depends on the value of PPC (bit 4) in
the HCSPARAMS register.
If PPC = logic 0 and PP = logic 1 — The Host Controller does not have
port power control switches. Always powered
If PPC = logic 1 and PP = logic 1 or logic 0 — The Host Controller has
port power control switches. This bit represents the current setting of the
switch: logic 0 = off, logic 1 = on. When PP is logic 0, the port is
nonfunctional and will not report any status
When an overcurrent condition is detected on a powered port and PPC is
logic 1, the PP bit in each affected port may be changed by the Host
Controller from logic 1 to logic 0, removing power from the port.
Line Status: This field reflects the current logical levels of the DP (bit 11)
and DM (bit 10) signal lines. These bits are used to detect low-speed USB
devices before the port reset and enable sequence. This field is valid only
when the Port Enable bit is logic 0, and the Current Connect Status bit is
set to logic 1.
00b — SE0: Not a low-speed device, perform EHCI reset
01b — K-state: Low-speed device, release ownership of port
10b — J-state: Not a low-speed device, perform EHCI reset
11b — Undefined: Not a low-speed device, perform EHCI reset
If the PP bit is logic 0, this field is undefined
-
Rev. 01 — 7 February 2007
Hi-Speed Universal Serial Bus PCI Host Controller
Port Number
1) where Port Number
SAF1562
© NXP B.V. 2007. All rights reserved.
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