SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 38

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
11.1.4 HcInterruptStatus register
Table 47.
This is a 4 B register that provides the status of the events that cause hardware interrupts.
The bit allocation of the register is given in
Controller sets the corresponding bit in this register. When a bit becomes set, a hardware
interrupt is generated, if the interrupt is enabled in the HcInterruptEnable register (see
Table
in this register by writing logic 1 to the bit positions to be cleared. The HCD may not set
any of these bits. The Host Controller does not clear the bit.
Table 48.
Address: Value read from func0 or func1 of address 10h + 0Ch
Bit
2
1
0
Bit
Symbol
Reset
Access
50) and the MIE (MasterInterruptEnable) bit is set. The HCD may clear specific bits
reserved
HcCommandStatus - Host Controller Command Status register bit description
…continued
HcInterruptStatus - Host Controller Interrupt Status register bit allocation
Symbol
BLF
CLF
HCR
R/W
31
0
[1]
Rev. 01 — 7 February 2007
Description
Bulk List Filled: This bit is used to indicate whether there are any
Transfer Descriptors (TDs) on the bulk list. It is set by the HCD whenever
it adds a TD to an ED in the bulk list. When the Host Controller begins to
process the head of the bulk list, it checks Bulk-Filled (BF). If BLF is
logic 0, the Host Controller does not need to process the bulk list. If BLF
is logic 1, the Host Controller needs to start processing the bulk list and
set BF to logic 0. If the Host Controller finds a TD on the list, then the
Host Controller needs to set BLF to logic 1, causing the bulk list
processing to continue. If no TD is found on the bulk list, and if the HCD
does not set BLF, then BLF is still logic 0 when the Host Controller
completes processing the bulk list and the bulk list processing stops.
Control List Filled: This bit is used to indicate whether there are any
TDs on the control list. It is set by the HCD whenever it adds a TD to an
ED in the control list.
When the Host Controller begins to process the head of the control list, it
checks CLF. If CLF is logic 0, the Host Controller does not need to
process the control list. If Control-Filled (CF) is logic 1, the Host
Controller needs to start processing the control list and set CLF to
logic 0. If the Host Controller finds a TD on the list, then the Host
Controller needs to set CLF to logic 1, causing the control list processing
to continue. If no TD is found on the control list, and if the HCD does not
set CLF, then CLF is still logic 0 when the Host Controller completes
processing the control list and the control list processing stops.
Host Controller Reset: This bit is set by the HCD to initiate a software
reset of the Host Controller. Regardless of the functional state of the Host
Controller, it moves to the USBSUSPEND state in which most of the
operational registers are reset, except those stated otherwise; for
example, IR (bit 8) in the HcControl register, and no host bus accesses
are allowed. This bit is cleared by the Host Controller on completing the
reset operation. The reset operation must be completed within 10 s.
This bit, when set, should not cause a reset to the Root Hub and no
subsequent reset signaling should be asserted to its downstream ports.
R/W
OC
30
0
R/W
29
0
Hi-Speed Universal Serial Bus PCI Host Controller
Table
R/W
28
0
48. When an event occurs, the Host
R/W
27
0
reserved
R/W
[1]
26
0
SAF1562
© NXP B.V. 2007. All rights reserved.
R/W
25
0
R/W
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24
0