SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 76

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
Table 107. PORTSC 1, 2 - Port Status and Control 1, 2 register bit description
Address: Value read from func2 of address 10h + 64h + (4
is 1, 2
Bit
8
7
Symbol
PR
SUSP
Description
Port Reset: Logic 1 means the port is in reset. Logic 0 means the port is
not in reset. Default = logic 0. When software sets this bit from logic 0, the
bus reset sequence as defined in Universal Serial Bus Specification
Rev. 2.0 is started. Software clears this bit to terminate the bus reset
sequence. Software must hold this bit at logic 1 until the reset sequence,
as specified in Universal Serial Bus Specification Rev. 2.0 , is completed.
Remark: When software sets this bit, it must also clear the Port Enable
bit.
Remark: When software clears this bit, there may be a delay before the bit
status changes to logic 0 because it will not read logic 0 until the reset is
completed. If the port is in high-speed mode after reset is completed, the
Host Controller will automatically enable this port; it can set the Port
Enable bit. A Host Controller must terminate the reset and stabilize the
state of the port within 2 ms of software changing this bit from logic 1 to
logic 0. For example, if the port detects that the attached device is
high-speed during a reset, then the Host Controller must enable the port
within 2 ms of software clearing this bit.
HCH (bit 12) in the USBSTS register must be logic 0 before software
attempts to use this bit. The Host Controller may hold Port Reset asserted
when the HCH bit is set.
Suspend: Default = logic 0. Logic 1 means the port is in the suspend
state. Logic 0 means the port is not suspended. The PED (Port Enabled)
bit and this bit define the port states as follows:
PED = logic 0 and SUSP = X — Port is disabled
PED = logic 1 and SUSP = logic 0 — Port is enabled
PED = logic 1 and SUSP = logic 1 — Port is suspended
When in the suspend state, downstream propagation of data is blocked on
this port, except for the port reset. If a transaction was in progress when
this bit was set, blocking occurs at the end of the current transaction. In the
suspend state, the port is sensitive to resume detection. The bit status
does not change until the port is suspended and there may be a delay in
suspending a port, if there is a transaction currently in progress on the
USB. Attempts to clear this bit are ignored by the Host Controller. The Host
Controller will unconditionally set this bit to logic 0 when:
If the host software sets this bit when the Port Enabled bit is logic 0, the
results are undefined.
Rev. 01 — 7 February 2007
•
•
Software changes the FPR (Force Port Resume) bit to logic 0
Software changes the PR (Port Reset) bit to logic 1
Hi-Speed Universal Serial Bus PCI Host Controller
[1]
[1]
Port Number
1) where Port Number
SAF1562
© NXP B.V. 2007. All rights reserved.
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