SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 39

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
[1]
Table 49.
Address: Value read from func0 or func1 of address 10h + 0Ch
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31
30
29 to 7
6
5
4
3
2
1
0
The reserved bits should always be written with the reset value.
Symbol
reserved
OC
reserved
RHSC
FNO
UE
RD
SF
WDH
SO
reserved
HcInterruptStatus - Host Controller Interrupt Status register bit description
R/W
R/W
R/W
23
15
0
0
7
0
[1]
Description
-
Ownership Change: This bit is set by the Host Controller when HCD sets
OCR (bit 3) in the HcCommandStatus register. This event, when
unmasked, will always immediately generate a System Management
Interrupt (SMI). This bit is forced to logic 0 when the SMI# pin is not
implemented.
-
Root Hub Status Change: This bit is set when the content of HcRhStatus
or the content of any of HcRhPortStatus[NumberofDownstreamPort] has
changed.
Frame Number Overflow: This bit is set when the MSB of HcFmNumber
(bit 15) changes value, or after the HccaFrameNumber is updated.
Unrecoverable Error: This bit is set when the Host Controller detects a
system error not related to USB. The Host Controller should not proceed
with any processing nor signaling before the system error is corrected. The
HCD clears this bit after the Host Controller is reset.
Resume Detected: This bit is set when the Host Controller detects that a
device on the USB is asserting resume signaling. This bit is set by the
transition from no resume signaling to resume signaling. This bit is not set
when the HCD sets the USBRESUME state.
Start-of-Frame: At the start of each frame, this bit is set by the Host
Controller and an SOF token is generated at the same time.
Writeback Done Head: This bit is immediately set after the Host Controller
has written HcDoneHead to HccaDoneHead. Further, updates of
HccaDoneHead occur only after this bit is cleared. The HCD should only
clear this bit after it has saved the content of HccaDoneHead.
Scheduling Overrun: This bit is set when USB schedules for current frame
overruns and after the update of HccaFrameNumber. A scheduling overrun
increments the SOC[1:0] field (bit 17 and bit 16 of HcCommandStatus).
Rev. 01 — 7 February 2007
RHSC
R/W
R/W
R/W
22
14
0
0
6
0
FNO
R/W
R/W
R/W
21
13
0
0
5
0
Hi-Speed Universal Serial Bus PCI Host Controller
R/W
R/W
R/W
UE
20
12
reserved
reserved
0
0
4
0
[1]
[1]
R/W
R/W
R/W
RD
19
11
0
0
3
0
R/W
R/W
R/W
SF
18
10
0
0
2
0
SAF1562
© NXP B.V. 2007. All rights reserved.
WDH
R/W
R/W
R/W
17
0
9
0
1
0
R/W
R/W
R/W
39 of 97
SO
16
0
8
0
0
0