SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet - Page 67

• Manufacturer Part Number: SAF1562HL
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SAF1562_1
Product data sheet
Table 94.
Address: Value read from func2 of address 10h + 24h
[1]
Table 95.
Address: Value read from func2 of address 10h + 24h
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 16
15
14
13
12
The reserved bits should always be written with the reset value.
USBSTS - USB Status register bit allocation
USBSTS - USB Status register bit description
R/W
R/W
ASS
R/W
Symbol
reserved
ASS
PSSTAT
RECL
HCH
31
23
15
R
0
0
0
7
0
reserved
PSSTAT
Rev. 01 — 7 February 2007
R/W
R/W
R/W
[1]
30
22
14
R
0
0
0
6
0
Description
-
Asynchronous Schedule Status: Default = logic 0. The bit reports the
current real status of the asynchronous schedule. If this bit is logic 0,
the status of the asynchronous schedule is disabled. If this bit is logic 1,
the status of the asynchronous schedule is enabled. The Host
Controller is not required to immediately disable or enable the
asynchronous schedule when software changes ASE (bit 5 in the
USBCMD register). When this bit and the ASE bit have the same value,
the asynchronous schedule is either enabled (1) or disabled (0).
Periodic Schedule Status: Default = logic 0. This bit reports the
current status of the periodic schedule. If this bit is logic 0, the status of
the periodic schedule is disabled. If this bit is logic 1, the status of the
periodic schedule is enabled. The Host Controller is not required to
immediately disable or enable the periodic schedule when software
changes PSE (bit 4) in the USBCMD register. When this bit and the
PSE bit have the same value, the periodic schedule is either enabled (1)
or disabled (0).
Reclamation: Default = logic 0. This is a read-only status bit that is
used to detect an empty asynchronous schedule.
HCHalted: Default = logic 1. This bit is logic 0 when RS (bit 0) in the
USBCMD register is logic 1. The Host Controller sets this bit to logic 1
after it has stopped executing because the RS bit is set to logic 0, either
by software or by the Host Controller hardware. For example, on an
internal error.
RECL
R/W
R/W
IAA
29
21
13
R
R
0
0
0
5
0
Hi-Speed Universal Serial Bus PCI Host Controller
HCH
HSE
R/W
R/W
R/W
28
20
12
R
0
0
1
4
0
reserved
reserved
R/W
R/W
R/W
R/W
[1]
[1]
FLR
27
19
11
0
0
0
3
0
PCD
R/W
R/W
R/W
R/W
26
18
10
2
0
0
0
0
reserved
SAF1562
ERRINT
© NXP B.V. 2007. All rights reserved.
USB
R/W
R/W
R/W
R/W
[1]
25
17
0
0
9
0
1
0
USBINT
R/W
R/W
R/W
R/W
67 of 97
24
16
0
0
8
0
0
0