PCM18XK1 Microchip Technology, PCM18XK1 Datasheet - Page 138

• Manufacturer Part Number: PCM18XK1
• Description: MODULE PROC PIC18F8680,6680,8565
• Manufacturer: Microchip Technology

Specifications of PCM18XK1

• Accessory Type: Processor Module
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICE2000
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
10.5
PORTE is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISE bit (= 0)
will make the corresponding PORTE pin an output (i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATE register
read and write the latched output value for PORTE.
PORTE is an 8-bit port with Schmitt Trigger input
buffers. Each pin is individually configurable as an input
or output. PORTE is multiplexed with the Enhanced
CCP module (Table 10-9).
On PIC18F8X8X devices, PORTE is also multiplexed
with the system bus as the external memory interface;
the I/O bus is available only when the system bus is
disabled by setting the EBDIS bit in the MEMCON
register (MEMCON<7>). If the device is configured in
Microprocessor or Extended Microcontroller mode, then
the PORTE<7:0> becomes the high byte of the address/
data bus for the external program memory interface. In
Microcontroller mode, the PORTE<2:0> pins become the
control inputs for the Parallel Slave Port when bit
PSPMODE
Section 4.1.1
Modes” for more information on program memory
modes.)
When the Parallel Slave Port is active, three PORTE
pins (RE0/RD/AD8, RE1/WR/AD9 and RE2/CS/AD10)
function as its control inputs. This automatically occurs
when the PSPMODE bit (PSPCON<4>) is set. Users
must also make certain that bits TRISE<2:0> are set to
configure the pins as digital inputs and the ADCON1
register is configured for digital I/O. The PORTE PSP
control functions are summarized in Table 10-9.
DS30491C-page 136
PORTE, TRISE and LATE
Registers
(PSPCON<4>)
“PIC18F8X8X
is
Program
set.
(Refer
Memory
to
Pin RE7 can be configured as the alternate peripheral
pin for the CCP2 module when the device is operating
in Microcontroller mode. This is done by clearing the
configuration bit, CCP2MX, in configuration register,
CONFIG3H (CONFIG3H<0>).
EXAMPLE 10-5:
CLRF
CLRF
MOVLW
MOVWF
Note:
PORTE
LATE
03h
TRISE
For PIC18F8X8X (80-pin) devices operat-
ing in other than Microcontroller mode,
PORTE defaults to the system bus on
Power-on Reset.
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE1:RE0 as inputs
; RE7:RE2 as outputs
INITIALIZING PORTE
 2004 Microchip Technology Inc.