PCM18XK1 Microchip Technology, PCM18XK1 Datasheet - Page 18

• Manufacturer Part Number: PCM18XK1
• Description: MODULE PROC PIC18F8680,6680,8565
• Manufacturer: Microchip Technology

Specifications of PCM18XK1

• Accessory Type: Processor Module
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICE2000
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
TABLE 1-2:
DS30491C-page 16
RD0/PSP0/AD0
RD1/PSP1/AD1
RD2/PSP2/AD2
RD3/PSP3/AD3
RD4/PSP4/AD4
RD5/PSP5/AD5
RD6/PSP6/AD6
RD7/PSP7/AD7
Legend: TTL
Note 1:
RD0
PSP0
AD0
RD1
PSP1
AD1
RD2
PSP2
AD2
RD3
PSP3
AD3
RD4
PSP4
AD4
RD5
PSP5
AD5
RD6
PSP6
AD6
RD7
PSP7
AD7
2:
3:
4:
5:
6:
7:
Pin Name
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
ST
I
P
Alternate assignment for CCP2 in all operating modes except Microcontroller – applies to PIC18F8X8X only.
Default assignment when CCP2MX is set.
External memory interface functions are only available on PIC18F8X8X devices.
CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is
multiplexed with either RB3 or RC1.
PORTH and PORTJ are only available on PIC18F8X8X (80-pin) devices.
PSP is available in Microcontroller mode only.
On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX
configuration bit.
PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED)
= TTL compatible input
= Schmitt Trigger input with CMOS levels
= Input
= Power
TQFP PLCC
PIC18F6X8X PIC18F8X8X
58
55
54
53
52
51
50
49
Pin Number
67
66
65
64
63
62
61
3
TQFP
72
69
68
67
66
65
64
63
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CMOS = CMOS compatible input or output
Analog = Analog input
O
OD
Buffer
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
ST
ST
ST
ST
ST
ST
ST
ST
= Output
= Open-Drain (no P diode to V
PORTD is a bidirectional I/O port. These
pins have TTL input buffers when external
memory is enabled.
Digital I/O.
Parallel Slave Port data.
External memory address/data 0.
Digital I/O.
Parallel Slave Port data.
External memory address/data 1.
Digital I/O.
Parallel Slave Port data.
External memory address/data 2.
Digital I/O.
Parallel Slave Port data.
External memory address/data 3.
Digital I/O.
Parallel Slave Port data.
External memory address/data 4.
Digital I/O.
Parallel Slave Port data.
External memory address/data 5.
Digital I/O.
Parallel Slave Port data.
External memory address/data 6.
Digital I/O.
Parallel Slave Port data.
External memory address/data 7.
 2004 Microchip Technology Inc.
Description
DD
)