PCM18XK1 Microchip Technology, PCM18XK1 Datasheet - Page 238

• Manufacturer Part Number: PCM18XK1
• Description: MODULE PROC PIC18F8680,6680,8565
• Manufacturer: Microchip Technology

Specifications of PCM18XK1

• Accessory Type: Processor Module
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICE2000
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
18.1.2
The enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 18-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal Baud Rate Generator is used
as a counter to time the bit period of the incoming serial
byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The auto-baud detect
must receive a byte with the value 55h (ASCII “U”,
which is also the LIN bus sync character) in order to
calculate the proper bit rate. The measurement is taken
over both a low and a high bit time in order to minimize
any effects caused by asymmetry of the incoming
signal. After a Start bit, the SPBRG begins counting up
using the preselected clock source on the first rising
edge of RX. After eight bits on the RX pin or the fifth
rising edge, an accumulated value totalling the proper
BRG period is left in the SPBRGH:SPBRG registers.
Once the 5th edge is seen (should correspond to the
Stop bit), the ABDEN bit is automatically cleared.
While calibrating the baud rate period, the BRG regis-
ters are clocked at 1/8th the preconfigured clock rate.
Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRG and SPBRGH will be used as
a 16-bit counter. This allows the user to verify that no
FIGURE 18-1:
DS30491C-page 236
BRG Value
BRG Clock
ABDEN bit
Note 1:
(Interrupt)
SPBRGH
RCIF bit
RCREG
SPBRG
RX pin
Read
AUTO-BAUD RATE DETECT
The ABD sequence requires the USART module to be configured in Asynchronous mode and WUE = 0.
Set by User
XXXXh
AUTOMATIC BAUD RATE CALCULATION
0000h
Start
Bit 0
XXXXh
XXXXh
Edge #1
Bit 1
Bit 2
Edge #2
carry occurred for 8-bit modes by checking for 00h in
the SPBRGH register. Refer to Table 18-4 for counter
clock rates to the BRG.
While the ABD sequence takes place, the USART state
machine is held in Idle. The RCIF interrupt is set once
the fifth rising edge on RX is detected. The value in the
RCREG needs to be read to clear the RCIF interrupt.
RCREG content should be discarded.
TABLE 18-4:
BRG16
Note:
Note 1: If the WUE bit is set with the ABDEN bit,
Bit 3
0
0
1
1
2: It is up to the user to determine that the
Bit 4
Edge #3
BRGH
During the ABD sequence, SPBRG and
SPBRGH are both used as a 16-bit
counter independent of BRG16 setting.
auto-baud rate detection will occur on the
byte following the break character.
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator fre-
quency and USART baud rates are not
possible due to bit error rates. Overall
system timing and communication baud
rates must be taken into consideration
when using the auto-baud rate detection
feature.
0
1
0
1
Bit 5
BRG COUNTER CLOCK
RATES
Bit 6
Edge #4
 2004 Microchip Technology Inc.
BRG Counter Clock
Bit 7
F
F
F
F
OSC
OSC
OSC
OSC
Stop Bit
Edge #5
/512
/128
/128
/32
Auto-Cleared
001Ch
1Ch
00h