LPC2478FBD208,551 NXP Semiconductors, LPC2478FBD208,551 Datasheet - Page 372
![IC ARM7 MCU 512K LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2478FBD208,551
Manufacturer Part Number
LPC2478FBD208,551
Description
IC ARM7 MCU 512K LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(91 pages)
2.OM11077.pdf
(792 pages)
3.OM11077.pdf
(10 pages)
4.LPC2478FBD208551.pdf
(89 pages)
Specifications of LPC2478FBD208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
Development Tools By Supplier
OM11015, OM11019, OM11022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4363
935284069551
LPC2478FBD208-S
935284069551
LPC2478FBD208-S
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC2478FBD208,551
Manufacturer:
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Quantity:
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- OM11077 PDF datasheet
- OM11077 PDF datasheet #2
- OM11077 PDF datasheet #3
- LPC2478FBD208551 PDF datasheet #4
- Current page: 372 of 792
- Download datasheet (5Mb)
NXP Semiconductors
12. USB device controller initialization
UM10237_4
User manual
Internally, there is a hardware FIFO status flag called Buffer_Full. This flag is set by the
Validate Buffer command and cleared when the data has been sent on the USB bus and
the buffer is empty.
A control IN buffer cannot be validated when its corresponding OUT buffer has the Packet
Over-written (PO) bit (see the Clear Buffer Register) set or contains a pending SETUP
packet. For the control endpoint the validated buffer will be invalidated when a SETUP
packet is received.
See
used.
The LPC2400 USB device controller initialization includes the following steps:
1. Enable the device controller by setting the PCUSB bit of PCONP.
2. Configure and enable the PLL and Clock Dividers to provide 48 MHz for usbclk, and
3. Enable the device controller clocks by setting DEV_CLK_EN and AHB_CLK_EN bits
4. Select the desired USB port pins using the USBPortSel register. The
5. Enable the USB pin functions by writing to the corresponding PINSEL register.
6. Disable the pull-up resistor on the V
7. Set USBEpIn and USBMaxPSize registers for EP0 and EP1, and wait until the
8. Enable endpoint interrupts (Slave mode):
9. Configure the DMA (DMA mode):
the desired frequency for cclk. For correct operation of synchronization logic in the
device controller, the minimum cclk frequency is 18 MHz. For the procedure for
determining the PLL setting and configuration, see
determining PLL
in the USBClkCtrl register. Poll the respective clock bits in the USBClkSt register until
they are set.
PORTSEL_CLK_EN bit must be set in USBClkCtrl before accessing USBPortSel and
should be cleared after accessing USBPortSel.
register.
EP_RLZED bit in USBDevIntSt is set so that EP0 and EP1 are realized.
– Clear all endpoint interrupts using USBEpIntClr.
– Clear any device interrupts using USBDevIntClr.
– Enable Slave mode for the desired endpoints by setting the corresponding bits in
– Set the priority of each enabled interrupt using USBEpIntPri.
– Configure the desired interrupt mode using the SIE Set Mode command.
– Enable device interrupts using USBDevIntEn (normally DEV_STAT, EP_SLOW,
– Disable DMA operation for all endpoints using USBEpDMADis.
– Clear any pending DMA requests using USBDMARClr.
Section 13–13 “Slave mode operation”
USBEpIntEn.
and possibly EP_FAST).
settings”.
Rev. 04 — 26 August 2009
BUS
Chapter 13: LPC24XX USB device controller
for a description of when this command is
pin using the corresponding PINMODE
Section 4–3.2.12 “Procedure for
UM10237
© NXP B.V. 2009. All rights reserved.
372 of 792
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