LPC2478FBD208,551 NXP Semiconductors, LPC2478FBD208,551 Datasheet - Page 77
LPC2478FBD208,551
Manufacturer Part Number
LPC2478FBD208,551
Description
IC ARM7 MCU 512K LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(91 pages)
2.OM11077.pdf
(792 pages)
3.OM11077.pdf
(10 pages)
4.LPC2478FBD208551.pdf
(89 pages)
Specifications of LPC2478FBD208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
Development Tools By Supplier
OM11015, OM11019, OM11022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4363
935284069551
LPC2478FBD208-S
935284069551
LPC2478FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP/恩智浦
Quantity:
20 000
- OM11077 PDF datasheet
- OM11077 PDF datasheet #2
- OM11077 PDF datasheet #3
- LPC2478FBD208551 PDF datasheet #4
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- Download datasheet (5Mb)
NXP Semiconductors
Table 67.
[1]
UM10237_4
User manual
Address
0xFFE0 8268
0xFFE0 826C EMCStatic WaitRd3
0xFFE0 8270
0xFFE0 8274
0xFFE0 8278
Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
Summary of EMC registers
Register Name
EMCStatic WaitOen3
EMCStatic WaitPage3
EMCStatic WaitWr3
EMCStatic WaitTurn3
10.1 EMC Control register (EMCControl - 0xFFE0 8000)
The EMCControl register is a read/write register that controls operation of the memory
controller. The control bits can be altered during normal operation.
bit assignments for the EMCControl register.
Table 68.
Bit
0
1
Symbol
EMC Enable (E)
Address mirror (M)
EMC Control register (EMCControl - address 0xFFE0 8000) bit description
…continued
Description
Selects the delay from chip select 3 or address change,
whichever is later, to output enable.
Selects the delay from chip select 3 to a read access.
Selects the delay for asynchronous page mode
sequential accesses for chip select 3.
Selects the delay from chip select 3 to a write access.
Selects the number of bus turnaround cycles for chip
select 3.
Rev. 04 — 26 August 2009
Value Description
0
1
0
1
Chapter 5: LPC24XX External Memory Controller (EMC)
Indicates if the EMC is enabled or disabled:
Disabled
Enabled (POR and warm reset value).
Disabling the EMC reduces power consumption.
When the memory controller is disabled the memory
is not refreshed. The memory controller is enabled by
setting the enable bit, or by reset.
This bit must only be modified when the EMC is in idle
state.
Indicates normal or reset memory map:
Normal memory map.
Reset memory map. Static memory CS1 is mirrored
onto CS0 and DYCS0 (POR reset value).
On POR, CS1 is mirrored to both CS0 and DYCS0
memory areas. Clearing the M bit enables CS0 and
DYCS0 memory to be accessed.
[1]
Table 5–68
Warm
Reset
Value
[1]
-
-
-
-
-
UM10237
© NXP B.V. 2009. All rights reserved.
POR
Reset
Value
[1]
0x0
0x1F
0x1F
0x1F
0xF
shows the
77 of 792
Reset
Value
1
1
Type
R/W
R/W
R/W
R/W
R/W
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