LPC2478FBD208,551 NXP Semiconductors, LPC2478FBD208,551 Datasheet - Page 427
LPC2478FBD208,551
Manufacturer Part Number
LPC2478FBD208,551
Description
IC ARM7 MCU 512K LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(91 pages)
2.OM11077.pdf
(792 pages)
3.OM11077.pdf
(10 pages)
4.LPC2478FBD208551.pdf
(89 pages)
Specifications of LPC2478FBD208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
Development Tools By Supplier
OM11015, OM11019, OM11022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4363
935284069551
LPC2478FBD208-S
935284069551
LPC2478FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP/恩智浦
Quantity:
20 000
- OM11077 PDF datasheet
- OM11077 PDF datasheet #2
- OM11077 PDF datasheet #3
- LPC2478FBD208551 PDF datasheet #4
- Current page: 427 of 792
- Download datasheet (5Mb)
NXP Semiconductors
UM10237_4
User manual
4.1 UARTn Receiver Buffer Register (U0RBR - 0xE000 C000, U2RBR -
4.2 UARTn Transmit Holding Register (U0THR - 0xE000 C000, U2THR -
4.3 UARTn Divisor Latch LSB Register (U0DLL - 0xE000 C000, U2DLL -
0xE007 8000, U3RBR - 0xE007 C000 when DLAB = 0, Read Only)
The UnRBR is the top byte of the UARTn Rx FIFO. The top byte of the Rx FIFO contains
the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” received data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in LCR must be zero in order to access the UnRBR.
The UnRBR is always Read Only.
Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.
the one that will be read in the next read from the RBR), the right approach for fetching the
valid pair of received byte and its status bits is first to read the content of the U0LSR
register, and then to read a byte from the UnRBR.
Table 378. UARTn Receiver Buffer Register (U0RBR - address 0xE000 C000,
0xE007 8000, U3THR - 0xE007 C000 when DLAB = 0, Write Only)
The UnTHR is the top byte of the UARTn TX FIFO. The top byte is the newest character in
the TX FIFO and can be written via the bus interface. The LSB represents the first bit to
transmit.
The Divisor Latch Access Bit (DLAB) in UnLCR must be zero in order to access the
UnTHR. The UnTHR is always Write Only.
Table 379. UART0 Transmit Holding Register (U0THR - address 0xE000 C000,
0xE007 8000, U3DLL - 0xE007 C000 when DLAB = 1) and UARTn
Divisor Latch MSB Register (U0DLM - 0xE000 C004, U2DLL -
0xE007 8004, U3DLL - 0xE007 C004 when DLAB = 1)
The UARTn Divisor Latch is part of the UARTn Baud Rate Generator and holds the value
used to divide the APB clock (PCLK) in order to produce the baud rate clock, which must
be 16× the desired baud rate. The UnDLL and UnDLM registers together form a 16 bit
divisor where UnDLL contains the lower 8 bits of the divisor and UnDLM contains the
Bit
7:0
Bit
7:0
Symbol
RBR
Symbol
THR
U2RBR - 0xE007 8000, U3RBR - 0E007 C000 when DLAB = 0, Read Only) bit
description
U2THR - 0xE007 8000, U3THR - 0xE007 C000 when DLAB = 0, Write Only) bit
description
Description
The UARTn Receiver Buffer Register contains the oldest
received byte in the UARTn Rx FIFO.
Description
Writing to the UARTn Transmit Holding Register causes the data
to be stored in the UARTn transmit FIFO. The byte will be sent
when it reaches the bottom of the FIFO and the transmitter is
available.
Rev. 04 — 26 August 2009
Chapter 16: LPC24XX UART0/2/3
UM10237
© NXP B.V. 2009. All rights reserved.
Reset Value
Undefined
Reset Value
NA
427 of 792
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