M30260F6AGP#U5A Renesas Electronics America, M30260F6AGP#U5A Datasheet - Page 181

• Manufacturer Part Number: M30260F6AGP#U5A
• Description: IC M16C MCU FLASH 48K 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30260F6AGP#U5A

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, PWM, Voltage Detect, WDT
• Number Of I /o: 39
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: UART
• Total Internal Ram Size: 2KB
• # I/os (max): 39
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: R8C
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 39
• Number Of Timers: 8
• For Use With: R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

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R
M
e
E
1
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J
6
NOTES:
UART2 transmission
output delay
0
Factor of interrupt number
10
(Refer to Fig.13.1.3.2.)
Functions of P7
Initial and end values of
SCL
Table 13.1.3.4. I
Factor of interrupt number
15
(Refer to Fig.13.1.3.2.)
Factor of interrupt number
16
1(Refer to Fig.13.1.3.2.)
Timing for transferring data
from the UART reception
shift register to the U2RB
register
Functions of P7
Functions of P7
Read RxD2 and SCL
levels
Initial value of TxD2 and
SDA
DMA1 factor (Refer to Fig.
14.1.3.2.)
Store received data
Read received data
Noise filter width
C
2
9
0 .
B
2 /
(1)
1. If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt
2. Set the initial value of SDA
3. Second data transfer to U2RB register (Rising edge of SCL
4. First data transfer to U2RB register (Falling edge of SCL
(1)
(1)
2
0
2
0
6
may inadvertently be set to 1 (interrupt requested). (Refer to “Notes on interrupts” in Usage Notes) If one of the bits
shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to clear
the IR bit to 0 (interrupt not requested) after changing those bits. SMD2 to SMD0 bits in the U2MR register, IICM bit
in the U2SMR register, IICM2 bit in the U2SMR2 register, CKPH bit in the U2SMR3 register
disabled).
2
outputs
A
0
F
Function
2
e
G
0 -
b
1 .
o r
2
0
, 5
u
0
0
1
2
p
2
pin
pin
pin
(
0
M
0
2
7
1
2
pin
6
C bus Mode Functions
C
page 162
2 /
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
1st to 8th bits are stored in
U2RB register bit 0 to bit 7
Clock synchronous serial I/O
mode (SMD2 to SMD0 = 001
IICM = 0)
UART2 transmission
Transmission started or
completed (selected by U2IRS)
Not delayed
RxD2 input
Possible when the
corresponding port direction bit
= 0
UART2 reception
U2RB register status is read
directly as is
UART2 reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
TxD2 output
CLK2 input or output selected
15ns
CKPOL = 0 (H)
CKPOL = 1 (L)
6
, A
M
2
1
output while the SMD2 to SMD0 bits in the U2MR register is set to ‘000
f o
6
C
3
2
2 /
9
6
, B
M
1
6
C
2
2 /
,
6
CKPH = 0
(No clock delay)
Start condition detection or stop condition detection
(Refer to Figure 13.1.3.2.1. STSPSEL Bit Function)
No acknowledgment
detection (NACK)
Rising edge of SCL
Acknowledgment detection
(ACK)
Rising edge of SCL
Delayed
The value set in the port register before setting I
(NACK/ACK interrupt)
Rising edge of SCL
SDA
SCL
Always possible no matter how the corresponding port direction bit is set
H
Acknowledgment detection
(ACK)
200ns
1st to 8th bits are stored in
U2RB register bit 7 to bit 0
) T
IICM2 = 0
I
2
C bus mode (SMD2 to SMD0 = 010
2
2
input/output
input/output
2
9th bit)
(Cannot be used in I
2
9th bit)
(Clock delay)
CKPH = 1
L
2
2
2
9th bit
9th bit
9th bit
UART2 transmission
Rising edge of
SCL
2
C mode)
1st to 7th bits are stored in U2RB register
bit 6 to bit 0, with 8th bit stored in U2RB
register bit 8
IICM2 = 1
(UART transmit/ receive interrupt)
CKPH = 0
(No clock delay)
UART2 transmission
Falling edge of SCL
Falling edge of
SCL
UART2 reception
Falling edge of SCL
H
2
9th bit
2
2
9th bit
, IICM = 1)
2
C bus mode
2
2
(Clock delay)
UART2 transmission
Falling edge of SCL
next to the 9th bit
1st to 8th bits are
stored in U2RB
register bit 7 to bit 0
(3)
Falling and rising
edges of SCL
bit
Read U2RB register
Bit 6 to bit 0 as bit 7
to bit 1, and bit 8 as
bit 0
CKPH = 1
9th bi
9th bit
L
2
’ (serial I/O
(4)
t
13. Serial I/O
(2)
2
9th
2